https://scholars.lib.ntu.edu.tw/handle/123456789/366791
標題: | A 0.89-mW 1-MHz 62-dB SNDR Continuous-Time Delta-Sigma Modulator with an Asynchronous Sequential Quantizer and Digital Excess Loop Delay Compensation | 作者: | C.-H. Weng C.-C. Lin Y.-C. Chang TSUNG-HSIEN LIN |
關鍵字: | Asynchronous circuits; Delta-sigma modulator; Digitally assisted design; Excess loop delay (ELD) | 公開日期: | 十二月-2011 | 卷: | 58 | 期: | 12 | 起(迄)頁: | 867-871 | 來源出版物: | IEEE TCAS-II | 摘要: | A second-order continuous-time delta-sigma modulator incorporating a proposed 4-bit asynchronous sequential quantizer and a digital excess-loop-delay (ELD) compensation technique is presented. The sequential operation of the proposed quantizer facilitates low power consumption while the hardware-efficient digital compensation technique allows the modulator to accommodate ELD. With a 1-MHz bandwidth and a 60-MHz sampling rate, the measured peak signal-to-noise-and-distortion ratio and dynamic range are 62 and 67 dB, respectively. Fabricated in a 90-nm CMOS, this chip consumes only 0.89 mW from a 1.2-V supply. © 2006 IEEE. |
URI: | http://scholars.lib.ntu.edu.tw/handle/123456789/366791 https://www.scopus.com/inward/record.uri?eid=2-s2.0-83655198349&doi=10.1109%2fTCSII.2011.2172709&partnerID=40&md5=872c9b617a0af5412bc6e23606124cd7 |
ISSN: | 15497747 | DOI: | 10.1109/TCSII.2011.2172709 | SDG/關鍵字: | Continuous time systems; Delay circuits; Delta sigma modulation; Energy efficiency; Signal to noise ratio; Asynchronous circuits; Compensation techniques; Delta sigma modulator; Digital compensation; Excess loop delays (ELD); Low-power consumption; Sequential operations; Signal to noise and distortion ratio; Modulators |
顯示於: | 電子工程學研究所 |
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