https://scholars.lib.ntu.edu.tw/handle/123456789/393059
標題: | A BiNoC architecture-aware task allocation and communication scheduling scheme | 作者: | Tsai, W.-C. Chen, W.-D. Lan, Y.-C. Hu, Y.-H. Chen, S.-J. SAO-JIE CHEN |
關鍵字: | Bidirectional link; Communication scheduling; Many-core; Network-on-Chip; Task allocation | 公開日期: | 2015 | 來源出版物: | Microprocessors and Microsystems | 摘要: | A novel real-time task allocation and scheduling scheme is proposed for a multi-core system incorporated in a Bidirectional Network-on-Chip (BiNoC) platform. Given a task graph, this scheme seeks to minimize the total execution time by allocating ready-to-execute tasks to as many available cores as possible subject to the real-time deadlines of each task. A refinement process is introduced to update the priority ranking of a task list so as to meet the timing constraints. In particular, the communication overhead is considered by incorporating the packet routing paths and delays into the overall optimization process. In doing so, the flexibility of bidirectional links of BiNoC is exploited to alleviate traffic congestion, such that more tasks could be executed concurrently at different cores and overall execution time be reduced. To validate the effectiveness of this proposed scheme, extensive simulations have been performed. The results clearly demonstrate the superior performance of this proposed scheme compared to existing approaches that did not exploit the flexibility of BiNoC. © 2015 Elsevier B.V. All rights reserved. |
URI: | http://www.scopus.com/inward/record.url?eid=2-s2.0-84954288347&partnerID=MN8TOARS http://scholars.lib.ntu.edu.tw/handle/123456789/393059 |
DOI: | 10.1016/j.micpro.2015.11.014 | SDG/關鍵字: | Microprocessor chips; Network-on-chip; Scheduling; Servers; Traffic congestion; VLSI circuits; Bi-directional links; Bidirectional networks; Communication overheads; Communication scheduling; Extensive simulations; Many core; Multi-core systems; Task allocation; Bins |
顯示於: | 電機工程學系 |
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