https://scholars.lib.ntu.edu.tw/handle/123456789/429349
標題: | Design of a Power-Efficient ARM Processor with a Timing-Error Detection and Correction Mechanism | 作者: | S. J. Chen G. Liu H. P. Yang C. H. Luo W. M. Hwu SAO-JIE CHEN |
關鍵字: | Error Correction; Error Detection; Error Resilience; Razor; Stochastic Processor; Surger | 公開日期: | 2016 | 來源出版物: | IEEE International System-on-Chip Conference (SOCC) | 摘要: | With the growing popularity of mobile devices, the trend in the field of system-on-chip has shifted from high performance to low power operation. However, traditional design methodology is limited by the design margins reserved for process, voltage and temperature variations. Therefore, a systematic solution that enables real-time timing error detection and correction was proposed to eliminate redundant margins in the design of an ARM microprocessor. A prototype stochastic ARM1136 processor was implemented in TSMC 90nm technology. Two circuit-level techniques, Razor and Surger, are exploited to form a hybrid error detection mechanism by observing both global and local timing information. To enable the deployment of aggressive voltage scaling with hardware-based error tolerance mechanism, we propose an activity-driven optimization flow to reshape the slack distribution based on path-activation probability. The chip achieves a frequency of 250MHz at worst case with 48.82mW power consumption. The overall power overhead of the proposed error tolerance mechanism is about 25% (hold-fixing latches 15.25% plus Razor 10.53%). The energy saving through design margins elimination is 51% (an average of the three corner cases) and a 42.8% saving was measured at the lowest operation voltage. © 2016 IEEE. |
URI: | https://scholars.lib.ntu.edu.tw/handle/123456789/429349 | ISSN: | 21641676 | DOI: | 10.1109/socc.2016.7905471 | SDG/關鍵字: | Application specific integrated circuits; ARM processors; Energy conservation; Error correction; Integrated circuit design; Probability distributions; Programmable logic controllers; Random processes; Stochastic systems; System-on-chip; Timing circuits; Voltage scaling; Activation probabilities; Aggressive voltage scaling; Error resilience; Error-detection mechanism; Process , voltage and temperatures; Razor; Stochastic Processor; Surger; Error detection |
顯示於: | 電機工程學系 |
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