https://scholars.lib.ntu.edu.tw/handle/123456789/499886
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Zeng, K.-H. | en_US |
dc.contributor.author | Kuan, T.-K. | en_US |
dc.contributor.author | SHEN-IUAN LIU | - |
dc.creator | Zeng, K.-H.;Kuan, T.-K.;Liu, S.-I. | - |
dc.date.accessioned | 2020-06-11T06:34:55Z | - |
dc.date.available | 2020-06-11T06:34:55Z | - |
dc.date.issued | 2015 | - |
dc.identifier.issn | 15497747 | - |
dc.identifier.uri | https://scholars.lib.ntu.edu.tw/handle/123456789/499886 | - |
dc.identifier.uri | https://www.scopus.com/inward/record.uri?eid=2-s2.0-84946839579&doi=10.1109%2fTCSII.2015.2455292&partnerID=40&md5=5a14ee9bcb258dbbb90761f7c33149a3 | - |
dc.description.abstract | A subharmonically injection-locked all-digital phase-locked loop (ADPLL) without a main divider is presented. It achieves not only low power but also low phase noise over the process, voltage, and temperature (PVT) variations. This ADPLL uses only a simple bang-bang phase detector without a time-to-digital converter when both frequency and phase locking. Moreover, the injection pulse can be self-adjusted to optimal timing over the PVT variations without additional calibration loop. This ADPLL is fabricated in a 40-nm CMOS process; it consumes 3.04 mW under a standard supply of 1.1 V excluding output buffers. The measured phase noise of the proposed ADPLL is -121.4 dBc/Hz at 1-MHz offset. The integrated RMS jitter is 109.6 fs for the offset frequency from 1 kHz to 100 MHz. The calculated figure-of-merit is equal to -254.39 dB. © 2015 IEEE. | - |
dc.relation.ispartof | IEEE Transactions on Circuits and Systems II: Express Briefs | - |
dc.subject | all-digital phase-locked loop; injection-locked; sub-harmonically | - |
dc.subject.other | Frequency converters; Phase locked loops; Phase noise; All digital phase locked loop; Bang-bang phase detectors; Figure of merits; Injection locked; Injection pulse; Offset frequencies; sub-harmonically; Time to digital converters; Phase comparators | - |
dc.title | A Subharmonically Injection-Locked All-Digital PLL Without Main Divider | en_US |
dc.type | journal article | en |
dc.identifier.doi | 10.1109/TCSII.2015.2455292 | - |
dc.identifier.scopus | 2-s2.0-84946839579 | - |
dc.relation.pages | 1033-1037 | - |
dc.relation.journalvolume | 62 | - |
dc.relation.journalissue | 11 | - |
item.fulltext | no fulltext | - |
item.openairecristype | http://purl.org/coar/resource_type/c_6501 | - |
item.cerifentitytype | Publications | - |
item.openairetype | journal article | - |
item.grantfulltext | none | - |
crisitem.author.dept | Electrical Engineering | - |
crisitem.author.dept | Electronics Engineering | - |
crisitem.author.dept | MediaTek-NTU Research Center | - |
crisitem.author.orcid | 0000-0002-3765-2948 | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | Others: University-Level Research Centers | - |
顯示於: | 電機工程學系 |
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