https://scholars.lib.ntu.edu.tw/handle/123456789/632141
標題: | Two-Way Transpose Multibit 6T SRAM Computing-in-Memory Macro for Inference-Training AI Edge Chips | 作者: | Su J.-W Si X Chou Y.-C Chang T.-W Huang W.-H Tu Y.-N Liu R Lu P.-J Liu T.-W Wang J.-H Chung Y.-L Ren J.-S Chang F.-C Wu Y Jiang H Huang S Li S.-H Sheu S.-S CHIH-I WU Lo C.-C Liu R.-S Hsieh C.-C Tang K.-T Yu S Chang M.-F. |
關鍵字: | Artificial intelligence; Backpropagation; Cloud computing; Common Information Model (computing); Resistance; Training; Transistors | 公開日期: | 2022 | 卷: | 57 | 期: | 2 | 起(迄)頁: | 609-624 | 來源出版物: | IEEE Journal of Solid-State Circuits | 摘要: | Computing-in-memory (CIM) based on SRAM is a promising approach to achieving energy-efficient multiply-and-accumulate (MAC) operations in artificial intelligence (AI) edge devices; however, existing SRAM-CIM chips support only DNN inference. The flow of training data requires that CIM arrays perform convolutional computation using transposed weight matrices. This article presents a two-way transpose (TWT) multiply cell with high resistance to process variation and a novel read scheme that uses input-aware zone prediction of maximum partial MAC values to enhance the signal margin for robust readout. A 28-nm 64-kb TWT CIM macro fabricated using foundry-provided compact 6T-SRAM cells achieved TAC of 3.8–21 ns and energy efficiency of 7–61.1 TOPS/W in performing MAC operations using 2–8-b inputs, 4–8-b weights, and 10–20-b outputs. © 2021 IEEE. |
URI: | https://www.scopus.com/inward/record.uri?eid=2-s2.0-85114736668&doi=10.1109%2fJSSC.2021.3108344&partnerID=40&md5=50aa14535a5e274c906e97f66c186ab9 https://scholars.lib.ntu.edu.tw/handle/123456789/632141 |
ISSN: | 00189200 | DOI: | 10.1109/JSSC.2021.3108344 | SDG/關鍵字: | Energy efficiency; Static random access storage; 6t sram cells; Energy efficient; High resistance; Multiply and accumulate operations; Process Variation; Signal margins; Training data; Weight matrices; Artificial intelligence |
顯示於: | 電機工程學系 |
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