https://scholars.lib.ntu.edu.tw/handle/123456789/632198
標題: | RF Performance Optimization of Stacked Si Nanosheet nFETs | 作者: | Lin H.-C Chou T Chiu K.-Y Chung C.-C Tsen C.-J CHEE-WEE LIU |
公開日期: | 2022 | 來源出版物: | 2022 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2022 | 摘要: | RF performance of stacked nanosheet (NS) nFETs is studied and optimized by validated TCAD simulation considering the 6-stack 4-finger transistor array layout and back-end-of-line (BEOL) up to M3 level. As compared to FinFETs, stacked NSs have larger effective width (Weff) under similar parasitic capacitance (Cpar), leading to better RF performance. In this work, the cut-off frequency (fT) and maximum oscillation frequency (fMAX) of Stacked NSs can achieve 435GHz and 405GHz by optimizing gate length (Lg) to 18nm, effective oxide thickness (EOT) to 0.8nm, suspension thickness (Tsus) to 7nm, and floor number (floor#) to 4. © 2022 IEEE. |
URI: | https://www.scopus.com/inward/record.uri?eid=2-s2.0-85130429316&doi=10.1109%2fVLSI-TSA54299.2022.9770993&partnerID=40&md5=a40f0a9f25fb8466d3d945c9f335f285 https://scholars.lib.ntu.edu.tw/handle/123456789/632198 |
DOI: | 10.1109/VLSI-TSA54299.2022.9770993 | SDG/關鍵字: | Capacitance; Floors; Silicon; Array layout; Back end of lines; Cut-off frequency (fT); Effective width; Large effective; Parasitics capacitance; Performance optimizations; RF performance; TCAD simulation; Transistor arrays; Nanosheets |
顯示於: | 電機工程學系 |
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