https://scholars.lib.ntu.edu.tw/handle/123456789/632210
標題: | Cell Stability and Write Improvement of 2T (Footprint) Stacked SRAM | 作者: | Chou T Chung C.-C Lin H.-C CHEE-WEE LIU |
公開日期: | 2022 | 來源出版物: | 2022 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2022 | 摘要: | Stacking 4 n-type vertical gate-all-around transistors (VFETs) on 2 pFinFETs can scale down a 6T SRAM bitcell into the footprint of only 2 transistors. The minimum operation voltage (Vmin) considering workfucntion (WF) variation can be reduced to 0.59V by tuning pFET fin height (Hfin) to 15nm and nFET gate length (Lgn) to 20nm without increasing bitcell area. Applying the negative bitline (NBL) level of -80mV can further increase the write speed by 10%. © 2022 IEEE. |
URI: | https://www.scopus.com/inward/record.uri?eid=2-s2.0-85130435762&doi=10.1109%2fVLSI-TSA54299.2022.9771031&partnerID=40&md5=78bbd501680b9b014a6b1f6011af6da7 https://scholars.lib.ntu.edu.tw/handle/123456789/632210 |
DOI: | 10.1109/VLSI-TSA54299.2022.9771031 | SDG/關鍵字: | 6T-SRAM; 6T-SRAMs; Bitcell; Cell stability; Fin height; Gate-all-around transistors; Gate-length; Operation voltage; Scale-down; Stackings |
顯示於: | 電機工程學系 |
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