https://scholars.lib.ntu.edu.tw/handle/123456789/633766
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Yu, Sheng Jung | en_US |
dc.contributor.author | Lee, Yu Chi | en_US |
dc.contributor.author | Lin, Liang Hsin | en_US |
dc.contributor.author | CHIA-HSIANG YANG | en_US |
dc.date.accessioned | 2023-07-17T06:50:05Z | - |
dc.date.available | 2023-07-17T06:50:05Z | - |
dc.date.issued | 2023-06-01 | - |
dc.identifier.issn | 00189200 | - |
dc.identifier.uri | https://scholars.lib.ntu.edu.tw/handle/123456789/633766 | - |
dc.description.abstract | This work presents the first cryptographic processor that supports the double ratchet protocol with backward secrecy for the Internet-of-Things (IoT) devices. A precomputation-based constant modular divider is used to reduce the area by 39.5% and energy consumption by 18.8%. A hash-based key derivative function (HKDF) module is proposed to reduce the energy consumption of the length selector by 89.8% and the energy consumption of the module by 35% by leveraging the characteristic of the input. A GF(24)2-based S-box is used to reduce the area of S-box by 21.2%. A 1-byte S-box is shared for key generation and text encryption/decryption to reduce the area by 46.8%. Fabricated in a 40-nm CMOS technology, the chip integrates 227k gates in 1.03 mm 2 and dissipates 1.18 mW at 16 MHz from a 0.56-V supply. The chip achieves a 211 734× lower energy consumption than the CPU solution. Compared with the state-of-the-art end-to-end protocol cryptographic processor, this work achieves an 18.5× higher energy efficiency for secure hash algorithm (SHA), 3× higher energy efficiency for advanced encryption standard (AES), and a 41% less energy for protocol establishment, with 10% smaller area. | en_US |
dc.relation.ispartof | IEEE Journal of Solid-State Circuits | en_US |
dc.subject | Backward secrecy | cryptographic processor | digital integrated circuit | double ratchet | end-to-end encryption | Internet of Things (IoT) | en_US |
dc.title | An Energy-Efficient Double Ratchet Cryptographic Processor With Backward Secrecy for IoT Devices | en_US |
dc.type | journal article | en |
dc.identifier.doi | 10.1109/JSSC.2022.3220838 | - |
dc.identifier.scopus | 2-s2.0-85142807829 | - |
dc.identifier.url | https://api.elsevier.com/content/abstract/scopus_id/85142807829 | - |
dc.relation.journalvolume | 58 | en_US |
dc.relation.journalissue | 6 | en_US |
dc.relation.pageend | 1819 | en_US |
item.openairetype | journal article | - |
item.openairecristype | http://purl.org/coar/resource_type/c_6501 | - |
item.cerifentitytype | Publications | - |
item.fulltext | no fulltext | - |
item.grantfulltext | none | - |
crisitem.author.dept | Electrical Engineering | - |
crisitem.author.dept | Electronics Engineering | - |
crisitem.author.orcid | 0000-0003-1163-321X | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
crisitem.author.parentorg | College of Electrical Engineering and Computer Science | - |
顯示於: | 電機工程學系 |
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