https://scholars.lib.ntu.edu.tw/handle/123456789/634454
標題: | A Sub-Sampling Phase-Locked Loop with a TDC-Based Frequency-Locked Loop | 作者: | Hong, Yu Meng TSUNG-HSIEN LIN |
關鍵字: | fast-locking | frequency-locked loop (FLL) | Phase-locked loop | sub-sampling | time-to-digital converter (TDC) | 公開日期: | 1-一月-2023 | 來源出版物: | 2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings | 摘要: | This paper presents an integer-N sub-sampling phase-locked loop (SSPLL), which proposes a novel TDC-based frequency-locked loop (FLL) to fast lock the output frequency. This SSPLL is fabricated in a 90-nm CMOS. With a 40-MHz reference input, the measured RMS jitter (10 kHz-100 MHz) at 2.4 GHz is 495.7 fs while the reference spur is -63.8 dBc. The total power consumption is 4.41 mW. The proposed FLL achieves the average frequency-locking time of about 160 ns only when simulated across various PVT settings and re-locking conditions. |
URI: | https://scholars.lib.ntu.edu.tw/handle/123456789/634454 | ISBN: | 9798350334166 | DOI: | 10.1109/VLSI-TSA/VLSI-DAT57221.2023.10134118 |
顯示於: | 電機工程學系 |
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