https://scholars.lib.ntu.edu.tw/handle/123456789/634455
標題: | A Sub-Sampling Phase-Locked Loop With a Robust Agile-Locking Frequency-Locked Loop | 作者: | Chen, Chia Min Hong, Yu Meng TSUNG-HSIEN LIN |
關鍵字: | frequency-locked loop (FLL) | integer-N PLL | phase noise | Phase-locked loop (PLL) | sub-sampling | 公開日期: | 1-一月-2023 | 來源出版物: | 2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings | 摘要: | This paper presents a sub-sampling phase-locked loop (SSPLL) with the proposed digital counter-based frequency-locked loop (FLL) to achieve agile and robust frequency locking. With a 20-MHz reference frequency, the measured SSPLL in-band phase noise at 2.42 GHz is -110 dBc/Hz; the reference spur is -50 dBc. Fabricated in a 90-nm CMOS and operated from a 1.2-V supply, the SSPLL including the proposed FLL consumes 14.5 mW while the power consumption is reduced to 3 mW when the FLL is turned off. Under a 500-mV VCO supply perturbation, the SSPLL returns to its stable locked frequency in about 5 μsec. |
URI: | https://scholars.lib.ntu.edu.tw/handle/123456789/634455 | ISBN: | 9798350334166 | DOI: | 10.1109/VLSI-TSA/VLSI-DAT57221.2023.10134200 |
顯示於: | 電機工程學系 |
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