https://scholars.lib.ntu.edu.tw/handle/123456789/640836
標題: | A Highly Multi-Bit Continuous-Time Delta-Sigma Modulator ADC with 9-Bit Feedback | 作者: | Wu, Jun Yi HSIN-SHU CHEN |
關鍵字: | analog-to-digital converter | continuous-time delta-sigma modulator | error feedback | mismatch shaping | successive-approximation-register | 公開日期: | 1-一月-2023 | 來源出版物: | Midwest Symposium on Circuits and Systems | 摘要: | This paper addresses the issues associated with multi-bit CT-DSM to significantly increase the number of bits within. A system architecture of CT-DSM, suitable for multi-bit quantizers and high-resolution feedback, is proposed. The employment of high-resolution feedback in CT-DSM improves stability, reduces the linearity requirements and power consumption of the amplifiers, and mitigates clock jitter sensitivity. A CT-DSM ADC utilizing 9-bit feedback DAC is presented. The proposed active-RC proportional-integrator-based loop filter, hybrid switched resistor-DAC, and an optimized metal-oxide-metal capacitor allow for an efficient design of highly multi-bit CT-DSM, thereby achieving low power consumption. The prototype chip is fabricated in TSMC 28nm CMOS process and occupies an active area of 0.063mm2. Clocked at 40 MHz, the modulator measures a 74.9 dB SNDR and 76.4 dB dynamic range within a 1.25 MHz bandwidth while consuming only 0.36mW from a single 0.9V supply, achieving a FOMs and FOMw of 170.4 dB and 32.2 fJ/conversion-step., respectively. |
URI: | https://scholars.lib.ntu.edu.tw/handle/123456789/640836 | ISBN: | 9798350302103 | ISSN: | 15483746 | DOI: | 10.1109/MWSCAS57524.2023.10405977 |
顯示於: | 電機工程學系 |
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