Browsing by Author "Chih-Fan Liao"
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Publication 40-Gb/s transimpedance-AGC amplifier and CDR circuit for broadband data receivers in 90nm CMOS(2008-03) ;Chih-Fan Liao; Chih-Fan Liao;Shen-Iuan LiuHigh-speed front-end amplifiers and CDR circuits play critical roles in broadband data receivers as the former needs to perform amplification at high data rate and the latter has to retime the data with the extracted low-jitter clock. In this paper, the design and experimental results of 40 Gb/s transimpedance-AGC amplifier and CDR circuit are described. The transimpedance amplifier incorporates reversed triple-resonance networks (RTRNs) and negative feedback in a common-gate configuration. A mathematical model is derived to facilitate the design and analysis of the RTRN, showing that the bandwidth is extended by a larger factor compared to using the shunt-series peaking technique, especially in cases when the parasitic capacitance is dominated by the next stage. Operating at 40 Gb/s, the amplifier provides an overall gain of 2 kΩ and a differential output swing of 520mVpp with BER < 10-9 for input spanning from 430μApp to 4mA pp. The measured integrated input-referred noise is 3.3μA rms. The half-rate CDR circuit employs a direction-determined rotary-wave quadrature VCO to solve the bidirectional-rotation problem in conventional rotary-wave oscillators. This guarantees the phase sequence while negligibly affecting the phase noise. With 40 Gb/s 231 - 1 PRBS input, the recovered clock jitter is 0.7psrms and 5.6pspp. The retimed data exhibits 13.3pspp jitter with BER < 10 -9. Fabricated in 90 nm digital CMOS technology, the overall amplifier consumes 75 mW and the CDR circuit consumes 48 mW excluding the output buffers, all from a 1.2 V supply. © 2008 IEEE.journal articleScopus© Citations 93 - Some of the metrics are blocked by yourconsent settings
Publication A 0.18μm CMOS receiver for 3.1 to 10.6GHz MB-OFDM UWB communication systems(2006-06) ;Yen-Horng Chen ;Chih-Wei Wang ;Ching-Feng Lee ;Jen-Lung Liu ;Tzu-Yi Yang ;Chih-Fan Liao ;Che-Fu Liang ;Gin-Kou Maconference paper2 - Some of the metrics are blocked by yourconsent settings
Publication A 10Gb/s CMOS automatic gain control amplifier with 35dB dynamic range for 10Gigabit Ethernet(2006-02) ;Chih-Fan Liaoconference paper1Scopus© Citations 28 - Some of the metrics are blocked by yourconsent settings
Publication A 40-Gb/s CMOS serial-link receiver with adaptive equalization and CDR(2008-02) ;Chih-Fan Liaoconference paper1Scopus© Citations 13 - Some of the metrics are blocked by yourconsent settings
Publication A 40-Gb/s CMOS serial-link receiver with adaptive equalization and clock/data recovery(2008-11) ;Chih-Fan Liaojournal article1Scopus© Citations 49 - Some of the metrics are blocked by yourconsent settings
Publication A 40Gb/s Transimpedance-AGC amplifier with 19dB DR in 90nm CMOS(2007-02) ;Chih-Fan Liaoconference paperScopus© Citations 20 - Some of the metrics are blocked by yourconsent settings
Publication A broadband noise-canceling CMOS LNA for 3.1-10.6-GHz UWB receivers(2007-02) ;Chih-Fan Liao; Chih-Fan Liao;Shen-Iuan LiuAn ultra-wideband 3.1-10.6-GHz low-noise amplifier employing a broadband noise-canceling technique is presented. By using the proposed circuit and design methodology, the noise from the matching device is greatly suppressed over the desired UWB band, while the noise from other devices performing noise cancellation is minimized by the systematic approach. Fabricated in a 0.18-μm CMOS process, the IC prototype achieves a power gain of 9.7 dB over a -3 dB bandwidth of 1.2-11.9-GHz and a noise figure of 4.5-5.1 dB in the entire UWB band. It consumes 20 m W from a 1.8-V supply and occupies an area of only 0.59 mm2. © 2007 IEEE.journal articleScopus© Citations 347