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在頑固性青光眼，並可能高度結膜下及鞏膜上纖維化的病人需施行 濾過手術時，用mitomycin C 輔助，已經在眼科界形成風潮(Chen 等, 1990; Hung 等, 1995)。青光眼濾過手術合併mitomycin C 使用，雖使手 術成功率大增(Bergstrom 等，1991; Pasquale 等，1992)，但這個方法並 不全然是沒有風險。最常見的的併發症之一就是持續性的術後眼壓過 低。術後眼壓過低可能是因為傷口癒合受阻，而導致房水流出過多 (Geijssen 等，1992; Jampel 等，1992; Schwartz 等，1992)。但是mitomycin C 對睫狀體的毒性而導致房水分泌的減少，也可能是造成持續性的術後 眼壓過低的原因。

A 10-bit 100-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) is presented by using the digital place-and-route (DPR) tools. The floorplan and blockage constraint for the bootstrapped switch and the comparator are presented to improve the parasitic capacitances caused by the DPR tools, respectively. The redundancy in the capacitive digital-to-analog converter (CDAC) and the on-chip reference buffer are presented to relieve the CDAC settling error. This calibration-free SAR ADC is fabricated in 40-nm CMOS technology and its active area is 0.0072 mm2. To compare with the full-custom method, the DPR flow has speeded up by a factor of 76 to complete the interconnection wires. Its power dissipation is 418-μ W at 100-MS/s and the calculated Walden FoM is 10.9-fJ/c. step at Nyquist frequency.

In the conventional PLL, the loop filter is composed of passive capacitor which occupies the most parts of chip area. As a result, PLL can save the area by replacing the passive capacitor which stores or releases the charges to a current-controlled oscillator and a dummy oscillator which store the phase information. To reduce the output phase noise, the letter adopts sub-sampling technique. As the loop locks the frequency and the phase difference between reference and divider output is less than 180°, the loop turns off the frequency-locked loop and the sub-sampling phase detector with higher gain dedicates on phase locking. Meanwhile, the loop turns off the divider path so as to avoid the divider from injecting phase noise into the system. However, the sub-sampling technique brings three side effects and lets the reference spur raise up. Hence, this thesis adopts spur reduction technique to alleviate those disadvantages from sub-sampling technique. The proposed PLL is fabricated in TSMC 90nm CMOS technology which active area is 0.02mm2 and provides 2GHz clock. The reference spur is -49.42 dBc and phase noise is -80.32 dBc/Hz at 1MHz offset from carrier frequency under 1.2V power supply with 8.68mW power dissipation.

A 20-Gb/s adaptive linear equalizer with a coefficient fast-converging method is presented. By using the asynchronous sampling technique, the power dissipation of the circuits, realizing the adaptation method, can be reduced. However, the equalization coefficients require a considerable amount of time to be determined. To shorten the asynchronous sampling time, the high-frequency gain of the linear equalizer is calibrated prior to the low-frequency one. With a 20-Gb/s pseudorandom binary sequence of 27-1, the measured bit-error-rates are all less than 10-12 for channel loss from-7.98 to-18.3 dB. Moreover, the equalization coefficients are determined within 2.68 μs . Fabricated in a 40-nm CMOS technology, this equalizer totally consumes 12.8 mW from a 1.1-V supply, of which only 4.9 mW dissipates in the circuits, realizing the proposed method. The calculated figure-of-merit is 0.035-pJ/bit/dB. © 2004-2012 IEEE.

This paper presents an on-chipSynchronous Inversion and Change Extraction (SICE) interface circuit, which combines the advantages of both the Synchronous Switch Harvesting on Inductor (SSHI) and Synchronous Electric Charge Extraction (SECE) interface circuits while utilizing a shared inductor. The SICE employs a bias-flip operation, similar to the SSHI, by inverting the piezoelectric voltage at each extremum multiple times to achieve higher power gain. Subsequently, SICE transfers all energy in Piezoelectric Harvester to the output capacitor, similar to the harvesting operation used in an SECE, thereby making the transferred energy independent of the loading impedance. A prototype AC-DC converter with the proposed SICE interface circuit was fabricated in a TSMC 0.25-μm process. Experimental results demonstrate an output power (POUT) of 130μW when the piezoelectric voltage (VPZ) is 10V. The SICE interface circuit has been theoretically and experimentally shown to harvest more than 624% compared to the conventional full-bridge rectifier, validating its superior performance.

This paper presents a 0.25μm HV-CMOS implementation of a Synchronous Inversion and Charge Extraction (SICE) interface circuit for piezoelectric energy harvesting. The bias-flip interfacing circuits which perform voltage inversion on the extremes of the voltage waveform have been proved effectively boosting the output power of piezoelectric energy harvesting. The proposed SICE interfacing circuit inverts the piezoelectric voltage on each extremum (bias flip action) for a given number of extremum occurrences, and then extracts the total electrostatic through the Synchronous Electric Charge Extraction (SECE) circuit. Thus, the SICE circuit is a combination of Synchronous Switch Harvesting on Inductor (SSHI) and the SECE circuits. It can achieve high power gain and be independent of loading impedance. The SICE interfacing circuit in TSMC 0.25μm HV-CMOS has been executed and taped-out. The post layout simulation results, including power consumption, circuit efficiency, and power gain will be presented in this paper. © 2018 IEEE.

An energy efficient delta-sigma time-to-digital converter (TDC) is presented in this paper. Compared with conventional circuit techniques, non-ideal effects associated with switching noise and transistor leakage can be generally prevented due to the use of a gated-free ring oscillator and leakage-suppression switches in the circuit implementation. The proposed TDC is fabricated in 90-nm CMOS, consuming a current of 5 μA from a 0.3-V supply. With first-order shaping of the quantization noise, the circuit demonstrates an equivalent number of bits (ENOB) of 10.9 bits in 50-kHz signal bandwidth. © 2017 IEEE.