公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2009 | Matching-based minimum-cost spare cell selection for design changes. | Jiang, Iris Hui-Ru; Chang, Hua-Yu; Chang, Liang-Gi; Hung, Huang-Bi; HUI-RU JIANG | Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009 | | | |
1999 | Noise-Constrained Performance Optimization by Simultaneous Gate and Wire Sizing Based on Lagrangian Relaxation. | Jiang, Iris Hui-Ru; Jou, Jing-Yang; HUI-RU JIANG ; YAO-WEN CHANG | Proceedings of the 36th Conference on Design Automation, New Orleans, LA, USA, June 21-25, 1999. | 9 | 0 | |
2012 | Opening: Introduction to CAD contest at ICCAD 2012: CAD contest. | Jiang, Iris Hui-Ru; Li, Zhuo; Li, Yih-Lang; HUI-RU JIANG | 2012 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2012, San Jose, CA, USA, November 5-8, 2012 | | | |
2000 | Optimal reliable crosstalk-driven interconnect optimization | Jiang, Iris Hui-Ru; Pan, Song-Ra; Chang, Yao-Wen; Jou, Jing-Yang; YAO-WEN CHANG | International Symposium on Physical Design | | | |
2000 | Optimal reliable crosstalk-driven interconnect optimization. | Jiang, Iris Hui-Ru; Pan, Song-Ra; Chang, Yao-Wen; HUI-RU JIANG ; YAO-WEN CHANG | Proceedings of the 2000 International Symposium on Physical Design, ISPD 2000, San Diego, CA, USA, April 9-12, 2000 | 7 | 0 | |
2013 | The overview of 2013 CAD contest at ICCAD. | Jiang, Iris Hui-Ru; Li, Zhuo; Wang, Hwei-Tseng; Viswanathan, Natarajan; HUI-RU JIANG | The IEEE/ACM International Conference on Computer-Aided Design, ICCAD'13, San Jose, CA, USA, November 18-21, 2013 | | | |
2014 | The overview of 2014 CAD contest at ICCAD. | Jiang, Iris Hui-Ru; Viswanathan, Natarajan; Chen, Tai-Chen; Li, Jin-Fu; HUI-RU JIANG | The IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2014, San Jose, CA, USA, November 3-6, 2014 | | | |
2006 | Reliable crosstalk-driven interconnect optimization. | Jiang, Iris Hui-Ru; Pan, Song-Ra; Chang, Yao-Wen; HUI-RU JIANG ; YAO-WEN CHANG | ACM Trans. Design Autom. Electr. Syst. | 0 | 2 | |
2003 | Simultaneous floorplanning and buffer block planning. | Jiang, Iris Hui-Ru; Chang, Yao-Wen; Jou, Jing-Yang; HUI-RU JIANG ; YAO-WEN CHANG | Proceedings of the 2003 Asia and South Pacific Design Automation Conference, ASP-DAC '03, Kitakyushu, Japan, January 21-24, 2003 | 0 | 0 | |
2011 | Simultaneous functional and timing ECO. | Chang, Hua-Yu; Jiang, Iris Hui-Ru; HUI-RU JIANG ; YAO-WEN CHANG | Proceedings of the 48th Design Automation Conference, DAC 2011, San Diego, California, USA, June 5-10, 2011 | 17 | 0 | |
2018 | Timing Macro Modeling for Efficient Hierarchical Timing Analysis. | Jiang, Iris Hui-Ru; Lee, Pei-Yu; HUI-RU JIANG | 2018 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018, Hong Kong, China, July 8-11, 2018 | | | |