公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2022 | Hardware Acceleration in Large-Scale Tensor Decomposition for Neural Network Compression | Kao, Chen Chien; Hsieh, Yi Yen; Chen, Chao Hung; CHIA-HSIANG YANG | Midwest Symposium on Circuits and Systems | 1 | 0 | |
2019 | A Hardware-Efficient ADMM-Based SVM Training Algorithm for Edge Computing. | Huang, Shuo-An; CHIA-HSIANG YANG | CoRR | | | |
2012 | Hardware-efficient EVD processor architecture in FastICA for epileptic seizure detection | CHIA-HSIANG YANG ; Shih, Y.-H.; Chen, T.-J.; Yang, C.-H.; Chiueh, H.; CHIA-HSIANG YANG | 2012 Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, APSIPA ASC 2012 | | | |
2012 | Hardware-efficient EVD processor architecture in FastICA for epileptic seizure detection. | Shih, Yi-Hsin; Chen, Tsan-Jieh; Yang, Chia-Hsiang; Chiueh, Herming; CHIA-HSIANG YANG | Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, APSIPA 2012, Hollywood, CA, USA, December 3-6, 2012 | | | |
2018 | A Hardware-Scalable DSP Architecture for Beam Selection in mm-Wave MU-MIMO Systems | C.-Y. Yeh; T.-C. Chu; C.-E. Chen; CHIA-HSIANG YANG | IEEE Transactions on Circuits and Systems I: Regular Paper | 3 | 3 | |
2021 | A High-Throughput FPGA Accelerator for Short-Read Mapping of the Whole Human Genome | Chen Y.-L; Chang B.-Y; CHIA-HSIANG YANG ; TZI-DAR CHIUEH | IEEE Transactions on Parallel and Distributed Systems | 8 | 15 | |
2021 | Hybrid Precoding Baseband Processor for 64x 64 Millimeter Wave MIMO Systems | Kao C; Chen C; CHIA-HSIANG YANG | IEEE Transactions on Circuits and Systems I: Regular Papers | | | |
2020 | Improved design and in vivo animal tests of bone-guided cochlear implant microsystem with monopolar biphasic multiple stimulation and neural action potential acquisition | Wang S.-H; Huang Y.-K; Chen C.-Y; Lee C.-F; Yang C.-H; Hung C.-C; Liu C.-H; Ker M.-D; CHIEN-HAO LIU ; CHIA-HSIANG YANG | 2020 IEEE Asian Solid-State Circuits Conference, A-SSCC 2020 | 3 | 0 | |
2019 | An integrated message-passing detector and decoder for polar-coded massive MU-MIMO systems | Chen, Y.-T.; Sun, W.-C.; Cheng, C.-C.; Tsai, T.-L.; Ueng, Y.-L.; CHIA-HSIANG YANG | IEEE Transactions on Circuits and Systems I: Regular Papers | | | |
2017 | Integration of Energy-Recycling Logic and Wireless Power Transfer for Ultra-Low-Power Implantables | H.-T. Lin; Y.-C. Wu; P.-H. Hsieh; C.-H. Yang; CHIA-HSIANG YANG | Int. Symposium Circuits and Systems (ISCAS) | 1 | 0 | |
2018 | Introduction to the Special Section on the 2017 Asian Solid-State Circuits Conference (A-SSCC) | Lin, T.-H.; Yang, C.-H.; TSUNG-HSIEN LIN ; CHIA-HSIANG YANG | IEEE Journal of Solid-State Circuits | 0 | 0 | |
2019 | Iterative Inter-Cell Interference Cancellation Receiver for LDPC-Coded MIMO Systems | Sun, W.-C.; Chen, Y.-T.; Yang, C.-H.; Ueng, Y.-L.; CHIA-HSIANG YANG | IEEE Transactions on Signal Processing | | | |
2020 | Iterative Receiver with a Lattice-Reduction-Aided MIMO Detector for IEEE 802.11ax | Wang Y.-P; Wen C.-C; Kao C.-C; Huang C.-J; Liu D.-Z; CHIA-HSIANG YANG | 2020 IEEE Global Communications Conference, GLOBECOM 2020 - Proceedings | | | |
2019 | An LDPC-Coded SCMA receiver with multi-user iterative detection and decoding | Sun, W.-C.; Su, Y.-C.; Ueng, Y.-L.; CHIA-HSIANG YANG | IEEE Transactions on Circuits and Systems I: Regular Papers | | | |
2018 | Massive MIMO detection VLSI design. | CHIA-HSIANG YANG | 2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Hsinchu, Taiwan, April 16-19, 2018 | | | |
2016 | Method and system for constrained power allocation in the multi-input multi-output systems | C.-H. Yang; C.-E. Chen; C.-W. Jou; CHIA-HSIANG YANG | | | | |
2019 | Micro-Architecture Optimization for Low-Power Bitcoin Mining ASICs. | Wang, Yu-Zhe; Wu, Jingjie; Chen, Shi-Hao; Chao, Mango Chia-Tso; CHIA-HSIANG YANG | International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2019, Hsinchu, Taiwan, April 22-25, 2019 | | | |
2016 | Multiple Input Multiple Output Wireless Communication System and Channel Decomposition Method Thereof | C.-H. Yang; Y.-C. Tsai; CHIA-HSIANG YANG | | | | |
2016 | Multiple Input Multiple Output Wireless Communication System and Channel Decomposition Method Thereof | C.-H. Yang; Y.-C. Tsai; CHIA-HSIANG YANG | | | | |
2018 | Performance of pre-production band 1 receiver for the Atacama Large Millimeter/submillimeter Array (ALMA) | Huang Y.-D.T; Morata O; Koch P.M; Kemper C; Hwang Y.-J; Chiong C.-C; Ho P.T.P; Chu Y.-H; Huang C.-D; Liu C.-T; Hsieh F.-C; Tseng Y.-H; CHIA-HSIANG YANG ; Tsay J.J; Chang T; Ho C.-T; Chiang P.-H; Chang C.-C; Jian S.-T; Hsu S.-P; Chien C; Iguchi S; Asayama S; Iono D; Gonzalez A; Effland J; Saini K; Pospieszalski M; Henke D; Yeung K; Finger R; Tapia V; Reyes N. | Proceedings of SPIE - The International Society for Optical Engineering | 5 | 0 | |