https://scholars.lib.ntu.edu.tw/handle/123456789/632697
標題: | Hardware Acceleration in Large-Scale Tensor Decomposition for Neural Network Compression | 作者: | Kao, Chen Chien Hsieh, Yi Yen Chen, Chao Hung CHIA-HSIANG YANG |
關鍵字: | canonical polyadic decomposition | hardware acceleration | Neural network compression | tensor decomposition | 公開日期: | 1-一月-2022 | 卷: | 2022-August | 來源出版物: | Midwest Symposium on Circuits and Systems | 摘要: | A tensor is a multi-dimensional array, which is embedded for neural networks. The multiply-accumulate (MAC) operations involved in a large-scale tensor introduces high computational complexity. Since the tensor usually features a low rank, the computational complexity can be largely reduced through canonical polyadic decomposition (CPD). This work presents an energy-efficient hardware accelerator that implements randomized CPD in large-scale tensors for neural network compression. A mixing method that combines the Walsh-Hadamard transform and discrete cosine transform is proposed to replace the fast Fourier transform with faster convergence. It reduces the computations for transformation by 83%. 75% of computations for solving the required least squares problem are also reduced. The proposed accelerator is flexible to support tensor decomposition with a size of up to 512\times 512\times 9\times 9. Compared to the prior dedicated processor for tensor computation, this work support larger tensors and achieves a 112\times lower latency given the same condition. |
URI: | https://scholars.lib.ntu.edu.tw/handle/123456789/632697 | ISBN: | 9781665402798 | ISSN: | 15483746 | DOI: | 10.1109/MWSCAS54063.2022.9859440 |
顯示於: | 電機工程學系 |
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