公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2012 | Multi-patch generation for multi-error logic rectification by interpolation with cofactor reduction. | Tang, Kai-Fu; Huang, Po-Kai; Chou, Chun-Nan; CHUNG-YANG HUANG | 2012 Design, Automation & Test in Europe Conference & Exhibition, DATE 2012, Dresden, Germany, March 12-16, 2012 | | | |
2015 | NBM-T-BBX-OS01, Semisynthesized from Osthole, Induced G1 Growth Arrest through HDAC6 Inhibition in Lung Cancer Cells | Pai, Jih-Tung; Hsu, Chia-Yun; Hua, Kuo-Tai; Yu, Sheng-Yung; Huang, Chung-Yang; Chen, Chia-Nan; Liao, Chiung-Ho; CHUNG-YANG HUANG | Molecules | 18 | 17 | |
2003 | Non-Assignable Signal Support During Formal Verification Of Circuit Designs | CHUNG-YANG HUANG | | | | |
2011 | Property-specific sequential invariant extraction for SAT-based unbounded model checking | Yeh, H.-H.; Wu, C.-Y.; CHUNG-YANG HUANG | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD | | | |
2007 | Propolin G, a prenylflavanone, isolated from Taiwanese propolis, induces caspase-dependent apoptosis in brain cancer cells | Huang, Wei-Jan; Huang, Chih-Hsiang; Wu, Chia-Li; Lin, Jen-Kun; Chen, Yue-Wen; Lin, Chun-Liang; Chuang, Shuang-En; Huang, Chung-Yang; Chen, Chia-Nan; CHUNG-YANG HUANG | Journal of Agricultural and Food Chemistry | | 65 | |
2007 | QuteIP: An IP Qualification Framework for System on Chip | Hsing-Chih Hung; Chi-Wen Chang; Tin-Hao Lin; CHUNG-YANG HUANG | IEEE SoC Conference (SOCC) | | | |
2012 | QuteRTL: Towards an open source framework for RTL design synthesis and verification | Yeh, H.-H.; Wu, C.-Y.; CHUNG-YANG HUANG | Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) | | | |
2007 | QuteSAT: A Robust Circuit-based SAT Solver for Complex Circuit Structure | Chi-An Wu; Ting-Hao Lin; Chih-Chun Lee; Chung-Yang (Ric) Huang; CHUNG-YANG HUANG | Design Automation and Test in Europe (DATE) Conference | | | |
2013 | A robust constraint solving framework for multiple constraint sets in constrained random verification | Wu, B.-H.; CHUNG-YANG HUANG | Proceedings - Design Automation Conference | | | |
2012 | A robust general constrained random pattern generator for constraints with variable ordering. | Wu, Bo-Han; CHUNG-YANG HUANG | 2012 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2012, San Jose, CA, USA, November 5-8, 2012 | | | |
2009 | SAT-controlled redundancy addition and removal: a novel circuit restructuring technique | Wu, Chi-An; Lin, Ting-Hao; Huang, Shao-Lun; Huang, Chung-Yang | Asia and South Pacific Design Automation Conference, 2009. ASP-DAC | 7 | 0 | |
2007 | Scalable Exploration of Functional Dependency by Interpolation and Incremental SAT Solving | Chih-Chun Lee; Jie-Hong R. Jiang; Chung-Yang Huang; Alan Mishchenko; CHUNG-YANG HUANG ; JIE-HONG JIANG | IEEE/ACM Int'l Conf. on Computer-Aided Design (ICCAD'07) | | | |
2012 | A semi-formal min-cost buffer insertion technique considering multi-mode multi-corner timing constraints | Tsai, S.-H.; Li, M.-Y.; CHUNG-YANG HUANG | Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC | | | |
2011 | SoC HW/SW Verification and Validation | CHUNG-YANG HUANG ; Yu-Fan Yin; Chih-Jen Hsu; Thomas B. Huang; Ting-Mao Chang | ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC) | 39 | 0 | |
1999 | Solving Constraint Satisfiability Problem for Automatic Generation of Design Verification Vectors | R.C.-Y. Huang; K.-T. Cheng; CHUNG-YANG HUANG | International High Level Design Validation and Test Workshop | | | |
2006 | Solving Constraint Satisfiability Problem For Automatic Generation of Design Verification Vectors | CHUNG-YANG HUANG | | | | |
2011 | Speeding Up MPSoC Virtual Platform Simulation by Ultra Synchronization Checking Method | Yu-Fu Yeh; Chung-Yang (Ric) Huang; Chi-An Wu; Hsin-Cheng Lin; CHUNG-YANG HUANG | ACM/IEEE Design, Automation, and Test in Europe (DATE) conference | | | |
2011 | Speeding Up MPSoC virtual platform simulation by Ultra Synchronization Checking Method. | Yeh, Yu-Fu; Huang, Chung-Yang; Wu, Chi-An; Lin, Hsin-Cheng; CHUNG-YANG HUANG | Design, Automation and Test in Europe, DATE 2011, Grenoble, France, March 14-18, 2011 | | | |
2008 | Speeding Up SoC Virtual Platform Simulation by Data-Dependency Aware Virtual Synchronization | Kuen-Huei Lin; Siao-Jie Cai Huang; CHUNG-YANG HUANG | International SoC Design Conference (ISoCC) | | | |
2010 | Speeding Up SoC Virtual Platform Simulation by Data-Dependency-Aware Synchronization and Scheduling | Kuen-Huei Lin; Siao-Jie Cai; CHUNG-YANG HUANG | ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC) | | | |