公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2017 | Recap of the 2017 International Symposium on Low Power Electronics and Design (ISLPED) | Garrett, D.; CHIA-LIN YANG | IEEE Design and Test | 0 | 0 | |
2005 | Reconfigurable platform for content science research | LIANG-GEE CHEN ; TEI-WEI KUO ; YAO-WEN CHANG ; SHAO-YI CHIEN ; CHIA-LIN YANG ; CHI-SHENG SHIH ; Ku, Mong-Kai | 11th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications | 0 | 0 | |
2023 | Reliable Brain-inspired AI Accelerators using Classical and Emerging Memories | Yayla, Mikail; Thomann, Simon; Islam, Md Mazharul; Wei, Ming Liang; Ho, Shu Yin; Aziz, Ahmedullah; CHIA-LIN YANG ; Chen, Jian Jia; Amrouch, Hussam | Proceedings of the IEEE VLSI Test Symposium | 0 | 0 | |
2022 | RM-SSD: In-Storage Computing for Large-Scale Recommendation Inference | Sun X; Wan H; Li Q; CHIA-LIN YANG ; TEI-WEI KUO ; Xue C.J. | Proceedings - International Symposium on High-Performance Computer Architecture | 9 | 0 | |
2021 | Robust Brain-Inspired Computing: On the Reliability of Spiking Neural Network Using Emerging Non-Volatile Synapses | Wei M.-L; Amrouch H; Sung C.-L; Lue H.-T; Yang C.-L; Wang K.-C; Lu C.-Y.; CHIA-LIN YANG | IEEE International Reliability Physics Symposium Proceedings | | | |
2011 | A SAT-based routing algorithm for cross-referencing biochips. | Yuh, Ping-Hung; Lin, Cliff Chiung-Yu; Huang, Tsung-Wei; Ho, Tsung-Yi; Yang, Chia-Lin; YAO-WEN CHANG ; CHIA-LIN YANG | 2011 International Workshop on System Level Interconnect Prediction, SLIP 2011, San Diego, CA, USA, June 5, 2011 | 10 | 0 | |
2015 | SECRET: A selective error correction framework for refresh energy reduction in DRAMs | CHIA-LIN YANG ; Lin, C.-H.; Shen, D.-Y.; Chen, Y.-J.; Yang, C.-L.; Wang, C.-Y.M.; CHIA-LIN YANG | ACM Transactions on Architecture and Code Optimization | | | |
2012 | SECRET: Selective error correction for refresh energy reduction in DRAMs. | Lin, Chung-Hsiang; Shen, De-Yu; Chen, Yi-Jung; Yang, Chia-Lin; CHIA-LIN YANG | 30th International IEEE Conference on Computer Design, ICCD 2012, Montreal, QC, Canada, September 30 - Oct. 3, 2012 | 37 | 0 | |
2003 | Smart cache: An energy-efficient D-cache for a software MPEG-2 video decoder | CHIA-LIN YANG ; Yang, Chia-Lin; Tseng, Hung-Wei; Ho, Chia-Chiang; CHIA-LIN YANG | 2003 Joint Conference of the 4th International Conference on Information, Communications and Signal Processing and 4th Pacific-Rim Conference on Multimedia | | | |
2007 | SoC System Design Program for Computer Science Majors | Shih, Chi-Sheng ; Yang, Chia-Lin ; Hung, Shih-Hao ; Hsueh, Chih-Wen ; Chen, Chuen-Liang; Kuo, Tei-Wei | 2007 Workshop on Embedded Systems Education | | | |
2005 | Software-controlled cache architecture for energy efficiency | Yang, Chia-Lin ; Tseng, Hung-Wei; Ho, Chia-Chiang; Wu, Ja-Ling; JA-LING WU | IEEE Transactions on Circuits and Systems for Video Technology | 8 | 3 | |
2006 | A Space-Efficient Caching Mechanism for Flash-Memory Address Translation | Wu, Chin-Hsien; Kuo, Tei-Wei ; Yang, Chia-Lin | IEEE 9th International Symposium on Object and component-oriented Real-time distributed Computing | 9 | 0 | |
2006 | A Space-Efficient Caching Mechanism for Flash-Memory Address Translation. | Wu, Chin-Hsien; Kuo, Tei-Wei; CHIA-LIN YANG ; TEI-WEI KUO | Ninth IEEE International Symposium on Object-Oriented Real-Time Distributed Computing (ISORC 2006), 24-26 April 2006, Gyeongju, Korea | 0 | 0 | |
2019 | Sparse ReRAM engine: Joint exploration of activation and weight sparsity in compressed neural networks | Yang, T.-H.; Cheng, H.-Y.; Yang, C.-L.; Tseng, I.-C.; Hu, H.-W.; Chang, H.-S.; CHIA-LIN YANG | Proceedings - International Symposium on Computer Architecture | 115 | 0 | |
2023 | Special Session-Non-Volatile Memories: Challenges and Opportunities for Embedded System Architectures with Focus on Machine Learning Applications | Henkel, Jorg; Siddhu, Lokesh; Bauer, Lars; Teich, Jurgen; Wildermann, Stefan; Tahoori, Mehdi; Mayahinia, Mahta; Castrillon, Jeronimo; Khan, Asif Ali; Farzaneh, Hamid; De Lima, Joao Paulo C.; Chen, Jian Jia; Hakert, Christian; Chen, Kuan Hsun; CHIA-LIN YANG ; Cheng, Hsiang Yun | Proceedings - 2023 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2023 | | | |
2015 | System-Level Performance and Power Optimization for MPSoC: A Memory Access-Aware Approach | Lin, Ye-Jyun; Yang, Chia-Lin; Huang, Jiao-We; Lin, Tay-Jyi; Hsueh, Chih-Wen; CHIA-LIN YANG ; CHIH-WEN HSUEH | Acm Transactions on Embedded Computing Systems | 4 | 3 | |
2009 | T-trees: A tree-based representation for temporal and three-dimensional floorplanning | Yuh, P.-H.; Yang, C.-L.; Chang, Y.-W.; YAO-WEN CHANG ; CHIA-LIN YANG | ACM Transactions on Design Automation of Electronic Systems | 6 | 3 | |
2011 | TACLC: Timing-aware cache leakage control for hard real-time systems | CHIA-LIN YANG ; Chen, Y.-J.; Yang, C.-L.; Chi, J.-W.; Chen, J.-J.; CHIA-LIN YANG | IEEE Transactions on Computers | | | |
2004 | Temporal Floorplanning Using 3D-subTCG | Yuh, Ping-Hung; Yang, Chia-Lin ; Chang, Yao-Wen ; Chen, Hsin-Lung | Asia and South Pacific Design Automation Conference, ASP-DAC | | | |
2004 | Temporal floorplanning using 3D-subTCG. | Yuh, Ping-Hung; Yang, Chia-Lin; Chang, Yao-Wen; CHIA-LIN YANG ; YAO-WEN CHANG | Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004 | 0 | 0 | |