公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
---|---|---|---|---|---|---|
2006 | A routability constrained scan chain ordering technique for test power reduction | X.-L. Huang; J.-L. Huang; JIUN-LANG HUANG | Asia and South Pacific Design Automation Conference | 8 | ||
2012 | A SAR ADC missing-decision level detection and removal technique | X.-L. Huang; J.-L. Huang; Y.-F. Chou; D.-M. Kwai; JIUN-LANG HUANG | VLSI Test Symposium | 0 | 0 | |
2010 | A scalable quantitative measure of IR-drop for scan pattern generation | M.-F. Wu; K.-H. Tsai; W.-T. Cheng; H.-C. Pan; J.-L. Huang; A. Kifli; JIUN-LANG HUANG | International Conference on Computer-Aided Design | 4 | 0 | |
2008 | A Segmented a-Si Gate Driver Design for Power Reduction and Floating Gate Line Stabilization | P.-H. Chiu; J.-L. Huang; JIUN-LANG HUANG | International Symposium on Flexible Electronics and Displays | |||
2011 | A self-testing and calibration method for embedded successive approximation register ADC | X.-L. Huang; P.-Y. Kang; H.-M. Chang; J.-L. Huang; Y.-F. Chou; Y.-P. Lee; D.-M. Kwai; C.-W. Wu; JIUN-LANG HUANG | Asia and South Pacific Design Automation Conference | 11 | 0 | |
2008 | A Self-Testing and Calibration Technique for Current-Steering DACs | Y.-L. Ma; J.-L. Huang; JIUN-LANG HUANG | International Symposium on VLSI Design, Automation, and Test | 4 | 0 | |
2009 | A Self-Testing Assisted Pipelined-ADC Calibration Technique | J.-L. Huang; X.-L. Huang; P.-Y. Kang; JIUN-LANG HUANG | International Conference on ASIC | |||
2015 | A Test-Application-Count Based Learning Technique for Test Time Reduction | G.-Y. Lin; K.-H. Tsai; J.-L. Huang; W.-T. Cheng; JIUN-LANG HUANG | International Symposium on VLSI Design, Automation, and Test | |||
2012 | A transition isolation scan cell design for low shift and capture power | Y.-T. Lin; J.-L. Huang; X. Wen; JIUN-LANG HUANG | Asian Test Symposium | 13 | 0 | |
2011 | ADC/DAC Loopback Linearity Testing by DAC Output Offsetting and Scaling | X.-L. Huang; J.-L. Huang; JIUN-LANG HUANG | IEEE Transactions on Very Large Scale Integration | 16 | 14 | |
2007 | An Efficient Peak Power Reduction Technique for Scan Testing | M.-F. Wu; K.-S. Hu; J.-L. Huang; JIUN-LANG HUANG | Asian Test Symposium | 18 | 0 | |
2010 | An Error Tolerance Scheme for 3D CMOS Imagers | H.-M. Sherman Chang; J.-L. Huang; D.-M. Kwai; K.-T. Tim Cheng; C.-W. Wu; JIUN-LANG HUANG | Design Automation Conference | 13 | 0 | |
2013 | An IDDQ-Based Source Driver IC Design-for-Test Technique | S.-S. Lin; C.-L. Kao; J.-L. Huang; C.-C. Lee; X.-L. Huang; JIUN-LANG HUANG | International Conference on Computer-Aided Design | 0 | 0 | |
2010 | An Improved Weight Assignment Scheme for IR-Drop-Aware At-Speed Scan Pattern Generation | M.-F. Wu; H.-C. Pan; T.-H. Wang; J.-L. Huang; K.-H. Tsai; W.-T. Cheng; JIUN-LANG HUANG | Asia and South Pacific Design Automation Conference | |||
2012 | An MCT-Based Bit-Weight Extraction Technique for Embedded SAR ADC Testing and Calibration | X.-L. Huang; J.-L. Huang; H.-I. Chen; C.-Y. Chen; K.-T. Tseng; M.-F. Huang; Y.-F. Chou; D.-M. Kwai; JIUN-LANG HUANG | Journal of Electronic Testing: Theory and Applications | 5 | 5 | |
2009 | An On-Chip Integrator Leakage Characterization Technique and Its Applications to Switched Capacitor Circuits Testing | C.-Y. Yang; X.-L. Huang; J.-L. Huang; JIUN-LANG HUANG | Asian Test Symposium | 1 | 0 | |
2006 | An On-Chip Jitter Generation Technique for SerDes Jitter Tolerance Testing | S.-W. Chang; J.-L. Huang; JIUN-LANG HUANG | VLSI Design/CAD Symposium | |||
2010 | A robust ADC code hit counting technique | J.-L. Huang; Kuo-Yu Chou; Ming-Huan Lu; Xuan-Lun Huang; JIUN-LANG HUANG | Design, Automation & Test in Europe | 1 | ||
2011 | Broadcast test pattern generation considering skew-insertion and partial-serial scan | C.-J. Lin; J.-L. Huang; JIUN-LANG HUANG | International Symposium on VLSI Design, Automation, and Test | 3 | 0 | |
2008 | Calibrating Capacitor Mismatch and Comparator Offset for 1-Bit/Stage Pipelined ADCs | X.-L. Huang; Y.-C. Yu; J.-L. Huang; JIUN-LANG HUANG | International Mixed-Signals, Sensors, and Systems Test Workshop | 6 | 0 |