公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
2008 | Simultaneous capture and shift power reduction test pattern generator for scan testing | Lin, H.-T.; Li, J.C.-M. | IET Computers & Digital Techniques | | | |
2013 | Test generation of path delay faults induced by defects in power TSV | Shih, C.-J.; Hsieh, S.-A.; Lu, Y.-C.; Li, J.C.-M.; Wu, T.-L.; TZONG-LIN WU ; YI-CHANG LU ; CHIEN-MO LI | Proceedings of the Asian Test Symposium | 2 | 0 | |
2019 | Test methodology for PCHB/PCFB Asynchronous Circuits | Shen, T.-Y.; Pai, C.-C.; Chen, T.-C.; Li, J.C.-M.; CHIEN-MO LI | Proceedings - International Test Conference | 1 | 0 | |
2018 | Test pattern compression for probabilistic circuits | Chang, C.-M.; Yang, K.-J.; Li, J.C.-M.; CHIEN-MO LI | Proceedings of the Asian Test Symposium | 0 | 0 | |
2016 | Test Pattern Modification for Average IR-Drop Reduction | Ding, W.-S.; Hsieh, H.-Y.; Han, C.-Y.; Li, J.C.-M.; Wen, X.; CHIEN-MO LI | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | | | |
2011 | Using launch-on-capture for testing scan designs containing synchronous and asynchronous clock domains | Wu, S.; Wang, L.-T.; Wen, X.; Jiang, Z.; Tan, L.; Zhang, Y.; Hu, Y.; Jone, W.-B.; Hsiao, M.S.; Li, J.C.-M.; Huang, J.-L.; JIUN-LANG HUANG ; CHIEN-MO LI | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 4 | 1 | |