Issue Date | Title | Author(s) | Source | scopus | WOS | Fulltext/Archive link |
2006 | Hierarchical value cache encoding for off-chip data bus. | Lin, Chung-Hsiang; Yang, Chia-Lin; King, Ku-Jei; CHIA-LIN YANG | Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006 | | | |
2004 | HotSpot cache: joint temporal and spatial locality exploitation for i-cache energy reduction. | Yang, Chia-Lin; Lee, Chien-Hao; CHIA-LIN YANG | Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004 | | | |
2018 | The impact of 2016 guideline on clinical practice for the management of hospital-acquired and ventilator-associated pneumonia in Taiwan | Yang, Chia-Lin; Chen, Yen-Fu; Lin, Chi-Ying; CHIA-LIN YANG | European Respiratory Journal | | | |
2005 | Joint exploration of architectural and physical design spaces with thermal consideration. | Wu, Yen-Wei; Yang, Chia-Lin; Yuh, Ping-Hung; CHIA-LIN YANG ; YAO-WEN CHANG | Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005 | 18 | 0 | |
2004 | Multiprocessor Energy-Efficient Scheduling with Task Migration Considerations. | Chen, Jian-Jia; Hsu, Heng-Ruey; Chuang, Kai-Hsiang; Yang, Chia-Lin; Pang, Ai-Chun; AI-CHUN PANG ; CHIA-LIN YANG ; TEI-WEI KUO | 16th Euromicro Conference on Real-Time Systems (ECRTS 2004), 30 June - 2 July 1004, Catania, Italy, Proceedings | 0 | 0 | |
2016 | Opportunities of Synergistically Adjusting Voltage-Frequency Levels of Cores and DRAMs in CMPs with 3D-Stacked DRAMs for Efficient Thermal Control | Chen, Yi-Jung; Yang, Chia-Lin; Lin, Pin-Sheng; Lu, Yi-Chang; CHIA-LIN YANG | Applied Computing Review | 5 | 0 | |
2010 | PM-COSYN: PE and memory co-synthesis for MPSoCs. | Chen, Yi-Jung; Yang, Chia-Lin; Wang, Po-Han; CHIA-LIN YANG | Design, Automation and Test in Europe, DATE 2010, Dresden, Germany, March 8-12, 2010 | | | |
2003 | A power-aware SWDR cell for reducing cache write power. | Chang, Yen-Jen; Yang, Chia-Lin; Lai, Feipei; CHIA-LIN YANG | Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003, Seoul, Korea, August 25-27, 2003 | | | |
2002 | A Programmable Memory Hierarchy for Prefetching Linked Data Structures. | Yang, Chia-Lin; Lebeck, Alvin R.; CHIA-LIN YANG | High Performance Computing, 4th International Symposium, ISHPC 2002, Kansai Science City, Japan, May 15-17, 2002, Proceedings | | | |
2008 | A progressive-ILP based routing algorithm for cross-referencing biochips. | Yuh, Ping-Hung; Sapatnekar, Sachin S.; Yang, Chia-Lin; CHIA-LIN YANG ; YAO-WEN CHANG | Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008 | 0 | 0 | |
2000 | Push vs. pull: Data movement for linked data structures | CHIA-LIN YANG ; Yang, Chia-Lin; Lebeck, Alvin R.; CHIA-LIN YANG | International Conference on Supercomputing | | | |
2000 | Push vs. pull: data movement for linked data structures. | Yang, Chia-Lin; Lebeck, Alvin R.; CHIA-LIN YANG | Proceedings of the 14th international conference on Supercomputing, ICS 2000, Santa Fe, NM, USA, May 8-11, 2000 | | | |
2011 | A SAT-based routing algorithm for cross-referencing biochips. | Yuh, Ping-Hung; Lin, Cliff Chiung-Yu; Huang, Tsung-Wei; Ho, Tsung-Yi; Yang, Chia-Lin; YAO-WEN CHANG ; CHIA-LIN YANG | 2011 International Workshop on System Level Interconnect Prediction, SLIP 2011, San Diego, CA, USA, June 5, 2011 | 10 | 0 | |
2012 | SECRET: Selective error correction for refresh energy reduction in DRAMs. | Lin, Chung-Hsiang; Shen, De-Yu; Chen, Yi-Jung; Yang, Chia-Lin; CHIA-LIN YANG | 30th International IEEE Conference on Computer Design, ICCD 2012, Montreal, QC, Canada, September 30 - Oct. 3, 2012 | 37 | 0 | |
2003 | Smart cache: An energy-efficient D-cache for a software MPEG-2 video decoder | CHIA-LIN YANG ; Yang, Chia-Lin; Tseng, Hung-Wei; Ho, Chia-Chiang; CHIA-LIN YANG | 2003 Joint Conference of the 4th International Conference on Information, Communications and Signal Processing and 4th Pacific-Rim Conference on Multimedia | | | |
2005 | Software-controlled cache architecture for energy efficiency | Yang, Chia-Lin ; Tseng, Hung-Wei; Ho, Chia-Chiang; Wu, Ja-Ling; JA-LING WU | IEEE Transactions on Circuits and Systems for Video Technology | 8 | 3 | |
2015 | System-Level Performance and Power Optimization for MPSoC: A Memory Access-Aware Approach | Lin, Ye-Jyun; Yang, Chia-Lin; Huang, Jiao-We; Lin, Tay-Jyi; Hsueh, Chih-Wen; CHIA-LIN YANG ; CHIH-WEN HSUEH | Acm Transactions on Embedded Computing Systems | 4 | 3 | |
2004 | Temporal floorplanning using 3D-subTCG. | Yuh, Ping-Hung; Yang, Chia-Lin; Chang, Yao-Wen; CHIA-LIN YANG ; YAO-WEN CHANG | Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004 | 0 | 0 | |
2004 | Temporal floorplanning using the T-tree formulation. | Yuh, Ping-Hung; Yang, Chia-Lin; CHIA-LIN YANG ; YAO-WEN CHANG | 2004 International Conference on Computer-Aided Design, ICCAD 2004, San Jose, CA, USA, November 7-11, 2004 | 0 | 0 | |
2009 | Thermal modeling for 3D-ICs with integrated microchannel cooling. | Mizunuma, Hitoshi; Yang, Chia-Lin; YI-CHANG LU ; CHIA-LIN YANG | 2009 International Conference on Computer-Aided Design, ICCAD 2009, San Jose, CA, USA, November 2-5, 2009 | 45 | 0 | |