公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
---|---|---|---|---|---|---|
1994 | A Test Clock Reduction Method for Scan-Designed Circuits | Chang, J. S.; 林呈祥; Lin, Chen-Shang | International Test Conference, Washington D.C.(1994.10) | |||
1994 | Test Time Reduction for Scan-Designed Circuits by Sliding Compatibility | Chang, J. S.; 林呈祥; Lin, Chen-Shang | Asian Test Symposium |