Issue Date | Title | Author(s) | Source | scopus | WOS | Fulltext/Archive link |
2019 | Accelerator Design for Vector Quantized Convolutional Neural Network | Wu, Y.-H.; Lee, H.; Lin, Y.S.; Chien, S.-Y.; SHAO-YI CHIEN | Proceedings 2019 IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2019 | 2 | 0 | |
2006 | Adaptive tile depth filter for the depth buffer bandwidth minimization in the low power graphics systems | Tsao, Y.-M.; Wu, C.-L.; Chien, S.-Y.; Chen, L.-G.; SHAO-YI CHIEN | IEEE International Symposium on Circuits and Systems | | | |
2013 | Algorithm adaptive video deinterlacing using self-validation framework | Wang, T.-C.; Liu, Y.-N.; Chien, S.-Y.; SHAO-YI CHIEN | IEEE International Symposium on Circuits and Systems | 1 | 0 | |
2014 | Algorithm and architecture design of high-quality video upscaling using database-free texture synthesis | Liu, Y.-N.; Lin, Y.-C.; Huang, Y.-L.; Chien, S.-Y.; SHAO-YI CHIEN | IEEE Transactions on Circuits and Systems for Video Technology | 7 | 5 | |
2011 | Algorithm and architecture design of image inpainting engine for video error concealment applications | Wu, G.-L.; Chen, C.-Y.; Chien, S.-Y.; SHAO-YI CHIEN ; Chen, Ching-Yi | IEEE Transactions on Circuits and Systems for Video Technology | 15 | 13 | |
2009 | Algorithm and architecture design of multi-layer video coding engine with hybrid scheme for wireless video links | Huang, K.-H.; Chen, H.-R.; Chien, S.-Y.; SHAO-YI CHIEN | 2009 IEEE International Conference on Multimedia and Expo, ICME 2009 | 0 | 0 | |
2017 | Algorithm and Architecture Design of Multirate Frame Rate Up-conversion for Ultra-HD LCD Systems | Huang, Y.-L.; Chen, F.-C.; Chien, S.-Y.; SHAO-YI CHIEN | IEEE Transactions on Circuits and Systems for Video Technology | 11 | 10 | |
2011 | Algorithm and architecture design of perception engine for video coding applications | Wu, G.-L.; Wu, T.-H.; Chien, S.-Y.; SHAO-YI CHIEN | IEEE Transactions on Multimedia | 10 | 6 | |
2006 | Algorithm and hardware architecture design for weighted prediction in H.264/MPEG-4 AVC | Tang, C.-S.; Tsai, C.-H.; Chien, S.-Y.; Chen, L.-G.; LIANG-GEE CHEN | IEEE International Symposium on Circuits and Systems | | | |
2007 | An 8.6mW 12.5Mvertices/s 800MOPS 8.91mm2 stream processor core for mobile graphics and video applications | Tsao, Y.-M.; Chang, C.-H.; Lin, Y.-C.; Chien, S.-Y.; Chen, L.-G.; LIANG-GEE CHEN ; Chien, Shao-Yi | IEEE Symposium on VLSI Circuits | 9 | 0 | |
2009 | An asynchronous fixed-coefficient fir filter implemented with FLEXIBLE a-si tft technology | Bai, J.-Y.; Chen, H.-R.; Chien, S.-Y.; SHAO-YI CHIEN | International Journal of Electrical Engineering | | | |
2002 | An efficient and low power architecture design for motion estimation using global elimination algorithm | Huang, Y.-W.; Chien, S.-Y.; Hsieh, B.-Y.; Chen, L.-G.; LIANG-GEE CHEN | ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing | | | |
2008 | An H.264/AVC scalable extension and high profile HDTV 1080p encoder chip | Chen, Y.-H.; Chuang, T.-D.; Chen, Y.-J.; Li, C.-T.; Hsu, C.-J.; Chien, S.-Y.; Chen, L.-G.; LIANG-GEE CHEN ; SHAO-YI CHIEN | IEEE Symposium on VLSI Circuits | 37 | 0 | |
2003 | Analysis and hardware architecture for global motion estimation in MPEG-4 advanced simple profile | Chien, S.-Y.; Chen, C.-Y.; Chao, W.-M.; Huang, Y.-W.; Chen, L.-G.; LIANG-GEE CHEN | IEEE International Symposium on Circuits and Systems | | | |
2008 | Architectural analyses of K-means silicon intellectual property for image segmentation | Chen, T.-W.; Sun, C.-H.; Bai, J.-Y.; Chen, H.-R.; Chien, S.-Y.; SHAO-YI CHIEN | IEEE International Symposium on Circuits and Systems | 19 | 0 | |
2011 | Architecture design and analysis of image-based rendering engine | Lai, J.-H.; Chen, C.-L.; Chien, S.-Y.; SHAO-YI CHIEN | IEEE International Conference on Multimedia and Expo | 2 | 0 | |
2010 | Architecture design of fine grain quality scalable encoder with CABAC for H.264/AVC scalable extension | Chuang, T.-D.; Chen, Y.-J.; Chen, Y.-H.; Chien, S.-Y.; Chen, L.-G.; LIANG-GEE CHEN ; SHAO-YI CHIEN | Journal of Signal Processing Systems | 3 | 1 | |
2007 | Architecture design of fine grain SNR scalable encoder with CABAC for H.264/AVC scalable extension | Chen, Y.-J.; Chen, Y.-H.; Chuang, T.-D.; Li, C.-T.; Chien, S.-Y.; Chen, L.-G.; LIANG-GEE CHEN ; SHAO-YI CHIEN | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | 3 | 0 | |
2007 | Automatic feature-based face scoring in surveillance systems | Chen, T.-W.; Hsu, S.-C.; Chien, S.-Y.; SHAO-YI CHIEN | 9th IEEE International Symposium on Multimedia, ISM 2007 | 12 | 0 | |
2014 | Automatic high dynamic range hallucination in inverse tone mapping | Kuo, P.-H.; Liang, H.-J.; Tang, C.-S.; Chien, S.-Y.; SHAO-YI CHIEN | 2014 IEEE International Workshop on Multimedia Signal Processing | 4 | 0 | |