公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
---|---|---|---|---|---|---|
2006 | High-Performance VLSI Architecture of Decision Feedback Equalizer for Gigabit Systems | Chih-Hsiu Lin; An-Yeu Wu; Fan-Min Li; AN-YEU(ANDY) WU ; 吳安宇 | IEEE Trans. Circuits and Systems, Part-II: Express Briefs | 22 | 18 | |
2005 | Soft-Threshold-Based MultiLayer Decision Feedback Equalizer (STM-DFE) Algorithm and VLSI Architecture | Chih-Hsiu Lin; A.-Y. Wu; AN-YEU(ANDY) WU ; 吳安宇 | IEEE Transactions on Signal Processing | 5 | 4 | |
2003 | VLSI Design of a Variable-Length FFT/IFFT Processor for OFDM-based Communication Systems | Jen-Chih Kuo; Ching-Hua Wen; Chih-Hsiu Lin; An-Yeu Wu; AN-YEU(ANDY) WU ; 吳安宇 | EURASIP Journal on Advances in Signal Processing | 45 | 33 |