公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
---|---|---|---|---|---|---|
2005 | A 0.1-25.5-GHz differential cascaded-distributed amplifier in 0.18-μm CMOS Technology | Chihun Lee; Lan-Chou Cho; Shen-Iuan Liu; SHEN-IUAN LIU | IEEE Asian Solid-State Circuits | 12 | 0 | |
2007 | A 1.2V 37-38.5GHz 8-phase clock generator in 0.13um CMOS technology | Lan-Chou Cho; Chihun Lee; Shen-Iuan Liu; SHEN-IUAN LIU | IEEE Journal of Solid-State Circuits | 4 | ||
2006 | A 1.2V 37-38.5GHz 8-phase clock generator in 0.13um CMOS technology | Chihun Lee; Lan-Cho Chou; Shen-Iuan Liu; Chun-Lin Ko; Ying-Zong Juang; Chin-Fong Chiu; SHEN-IUAN LIU | 2006 Symposium on VLSI Circuits | 4 | 0 | |
2007 | A 33.6-to-33.8Gb/s burst-mode CDR in 90nm CMOS | Lan-Chou Cho; Chihun Lee; Shen-Iuan Liu; SHEN-IUAN LIU | International Solid-State Circuits Conference (ISSCC) 2007 | 7 | 0 | |
2009 | A 33.6-to-33.8Gb/s burst-mode CDR in 90nm CMOS technology | Lan-Chou Cho; Chihun Lee; Chao-Ching Hung; Shen-Iuan Liu; SHEN-IUAN LIU | IEEE Journal of Solid-State Circuits | |||
2006 | A 35-Gb/s limiting amplifier in 0.13um CMOS technology | Chihun Lee; Shen-Iuan Liu; SHEN-IUAN LIU | 2006 Symposium on VLSI Circuits | 6 | 0 | |
2006 | A 44GHz dual-modulus divide-by-4/5 prescaler in 90nm CMOS technology | Chihun Lee; Lan-Chou Cho; Shen-Iuan Liu; SHEN-IUAN LIU | IEEE Custom Integrated Circuits Conference | 10 | 0 | |
2008 | A 50.8-53-GHz clock generator using a harmonic-locked PD in 0.13-μm CMOS | Chihun Lee; Lan-Chou Cho; Jia-Hao Wu; SHEN-IUAN LIU | IEEE Transactions on Circuits and Systems II: Express Briefs | 8 | 7 | |
2008 | A 57.1-59GHz CMOS fractional-N frequency synthesizer using quantization noise shifting technique | Chao-Ching Hung; Chihun Lee; Lan-Chou Cho; Shen-Iuan Liu; SHEN-IUAN LIU | IEEE Asian Solid-State Circuits Conference (A-SSCC) | 0 | 0 | |
2007 | A 58-to-60.4GHz frequency synthesizer in 90nm CMOS | Chihun Lee; Shen-Iuan Liu; SHEN-IUAN LIU | International Solid-State Circuits Conference (ISSCC) 2007 | 74 | 0 | |
2008 | A dual-band 61.4~63GHz/ 75.5~77.5GHz CMOS receiver in a 90nm technology | Ke-Hou Chen; Chihun Lee; Shen-Iuan Liu; SHEN-IUAN LIU | 2008 Symposium on VLSI Circuits | 9 | 0 |