公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 |
---|---|---|---|---|---|---|
2006 | A systematic design to suppress wideband ground bounce noise in high-speed circuits by electromagnetic bandgap enhanced split powers | C.-L. Wang; G.-H. Shiue; W.-D. Guo; R.-B. Wu; RUEY-BEEI WU | IEEE Transactions on Microwave Theory and Techniques | 48 | 42 | |
2006 | An efficient and flexible modeling for power/ground planes | K.-B. Wu; G.-H. Shiue; W.-D. Guo; C.-M. Lin; R.-B. Wu; RUEY-BEEI WU | 14th Topical Meeting on Electrical Performance of Electronic Packaging, EPEP | 1 | 0 | |
2007 | An integrated signal and power integrity analysis for signal traces through the parallel planes using hybrid finite-element and finite-difference time-domain techniques | W.-D. Guo; G.-H. Shiue; C.-M. Lin; RUEY-BEEI WU | IEEE Transactions on Advanced Packaging | 18 | 15 | |
2005 | Combined FDTD/FETD algorithm for ground bounce characterization of differential traces through the planes | W.-D. Guo; G.-H. Shiue; C.-M. Lin; R.-B. Wu; RUEY-BEEI WU | IEEE 14th Topical Meeting on Electrical Performance of Electronic Packaging | 0 | 0 | |
2006 | Comparisons between serpentine and flat spiral delay lines on transient reflection/transmission waveforms and eye diagrams | W.-D. Guo; G.-H. Shiue; C.-M. Lin; RUEY-BEEI WU | IEEE Transactions on Microwave Theory and Techniques | 43 | 40 | |
2008 | Delaunay–Voronoi Modeling of Power-Ground Planes With Source Port Correction | K.-B. Wu; G.-H. Shiue; W.-D. Guo; C.-M. Lin; R.-B. Wu; RUEY-BEEI WU | IEEE Transactions on Advanced Packaging | 43 | 33 | |
2006 | Design of wideband impedance matching for through-hole via transition using ellipse-shaped anti-pad | W.-D. Guo; W.-N. Chine; C.-L. Wang; G.-H. Shiue; R.-B. Wu; RUEY-BEEI WU | 14th Topical Meeting on Electrical Performance of Electronic Packaging, EPEP | 18 | 0 | |
2010 | Enhanced microstrip guard trace for ringing noise suppression using a dielectric superstrate | Y.-S. Cheng; W.-D. Guo; C.-P. Hung; RUEY-BEEI WU ; D. De Zutter | IEEE Transactions on Advanced Packaging | 26 | 16 | |
2008 | Fewest vias design for microstrip guard trace by using overlying dielectric | Y.-S. Cheng; W.-D. Guo; G.-H.Shiue; H.-H. Cheng; C.-C. Wang; R.-B. Wu; RUEY-BEEI WU | IEEE 17th Topical Meeting on Electrical Performance of Electronic Packaging | 18 | 0 | |
2010 | Guard trace design for improvement on transient waveforms and eye diagrams of serpentine delay lines | G.-H. Shiue; C.-Y. Chao; W.-D. Guo; R.-B. Wu; RUEY-BEEI WU | IEEE Transactions on Advanced Packaging | 24 | 20 | |
2008 | Placement of shorting vias for power integrity in multi-layered structures | S.-H. Hsu; Y.-S. Cheng; W.-D. Guo; H.-H. Cheng; C.-C. Wang; R.-B. Wu; RUEY-BEEI WU | IEEE 17th Topical Meeting on Electrical Performance of Electronic Packaging | 0 | 0 | |
2008 | Reflection enhanced compensation of lossy traces for best eye-diagram improvement using high-impedance mismatch | W.-D. Guo; F.-N. Tsai; G.-H. Shiue; R.-B. Wu; RUEY-BEEI WU | IEEE Transactions on Advanced Packaging | 23 | 19 | |
2008 | Signal integrity analysis of DDR3 high-speed memory module | C.-K. Chen; W.-D. Guo; C.-H. Yu; R.-B. Wu; RUEY-BEEI WU | 2008 Electrical Design of Advanced Packaging and Systems Symposium | 12 | 0 |