Issue Date | Title | Author(s) | Source | scopus | WOS | Fulltext/Archive link |
2003 | A high-performance/low-latency vector rotational CORDIC architecture based on extended elementary angle set and trellis-based searching schemes | AN-YEU(ANDY) WU ; Wu, Cheng-Shing; Wu, An-Yeu; Lin, Chih-Hsiu; AN-YEU(ANDY) WU | IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing | | | |
1995 | Algorithm-based low-power DSP system design: Methodology and verification | AN-YEU(ANDY) WU ; Wu, An-Yeu; Liu, K.J.Ray; Zhang, Zhongying; Nakajima, Kazuo; Raghupathy, Arun; Liu, Shang-Chieh; AN-YEU(ANDY) WU | IEEE Workshop on VLSI Signal Processing | | | |
1995 | Algorithm-based low-power transform coding architectures | AN-YEU(ANDY) WU ; Wu, An-Yeu; Liu, K.J.Ray; AN-YEU(ANDY) WU | ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing | | | |
1995 | Algorithm-based low-power transform coding architectures. | Wu, An-Yeu; Liu, K. J. Ray; AN-YEU(ANDY) WU | 1995 International Conference on Acoustics, Speech, and Signal Processing, ICASSP '95, Detroit, Michigan, USA, May 08-12, 1995 | | | |
1998 | Computationally efficient fast algorithm and architecture for the IFFT/FFT in DMT/OFDM systems | AN-YEU(ANDY) WU ; Wu, An-Yeu; Chan, Tsun-Shan; AN-YEU(ANDY) WU | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | | | |
1998 | Cost-efficient parallel lattice VLSI architecture for the IFFT/FFT in DMT transceiver technology | AN-YEU(ANDY) WU ; Wu, An-Yeu; Chan, Tsun-Shan; AN-YEU(ANDY) WU | ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing | | | |
1998 | Cost-efficient parallel lattice VLSI architecture for the IFFT/FFT in DMT transceiver technology. | Wu, An-Yeu; Chan, Tsun-Shan; AN-YEU(ANDY) WU | Proceedings of the 1998 IEEE International Conference on Acoustics, Speech and Signal Processing, ICASSP '98, Seattle, Washington, USA, May 12-15, 1998 | | | |
2006 | DSP engine design for LINC wireless transmitter systems. | Jheng, Kai-Yuan; Wang, Yi-Chiuan; Wu, An-Yeu; HEN-WAI TSAO ; AN-YEU(ANDY) WU | International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece | 0 | 0 | |
2007 | Ensemble Dependent Matrix Methodology for Probabilistic-Based Fault-tolerant Nanoscale Circuit Design. | Rao, Huifei; Chen, Jie; Yu, Changhong; Ang, Woon Tiong; Wey, I-Chyn; Wu, An-Yeu; Zhao, Hong; AN-YEU(ANDY) WU | International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA | | | |
1998 | Fast algorithm for reduced-complexity programmable DSP implementation of the IFFT/FFT in DMT systems | AN-YEU(ANDY) WU ; Wu, An-Yeu; Chan, Tsun-Shan; Wang, Bowen; AN-YEU(ANDY) WU | IEEE Global Telecommunications Conference | | | |
1994 | Low-power and low-complexity DCT/IDCT VLSI architecture based on backward chebyshev recursion | AN-YEU(ANDY) WU ; Wu, An-Yeu; Liu, K.J.Ray; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | | | |
1994 | A Low-Power and Low-Complexity DCT/IDCT VLSI Architecture Based On Backward Chebyshev Recursion. | Wu, An-Yeu; Liu, K. J. Ray; AN-YEU(ANDY) WU | 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30 - June 2, 1994 | | | |
1996 | Low-power design methodology for DSP systems using multirate approach | AN-YEU(ANDY) WU ; Wu, An-Yeu; Ray Liu, K.J.; Zhang, Zhongying; Nakajima, Kazuo; Raghupathy, Arun; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | | | |
1998 | Optimal fixed-point VLSI structure of a floating-point based digital filter design | AN-YEU(ANDY) WU ; Wu, An-Yeu; Hwang, Kuo-Fuo; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | | | |
1996 | Parallel programmable video co-processor design | AN-YEU(ANDY) WU ; Wu, An-Yeu; Ray Liu, K.J.; Raghupathy, Arun; Liu, Shang-Chieh; AN-YEU(ANDY) WU | IEEE International Conference on Image Processing | | | |
1995 | Parallel programmable video co-processor design. | Wu, An-Yeu; Liu, K. J. Ray; Raghupathy, Arun; Liu, Shang-Chieh; AN-YEU(ANDY) WU | Proceedings 1995 International Conference on Image Processing, Washington, DC, USA, October 23-26, 1995 | | | |
2007 | A Power-Aware Reconfigurable Rendering Engine Design with 453MPixels/s, 16.4MTriangles/s Performance. | Chao, Chih-Hao; Kuo, Yen-Lin; Wu, An-Yeu; Chien, Weber; AN-YEU(ANDY) WU | International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA | | | |
2007 | Reconfigurable Color Doppler DSP Engine for High-Frequency Ultrasonic Imaging Systems. | Yu, Tzu-Hao; Sun, Shih-Yu; Ding, Chih-Liang; Li, Pai-Chi; Wu, An-Yeu; PAI-CHI LI ; AN-YEU(ANDY) WU | Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2007, Proceedings, October 17-19, 2007, Eton Hotel, Shanghai, China | 8 | 0 | |
2015 | Regional ACO-Based Cascaded Adaptive Routing for Traffic Balancing in Mesh-Based Network-on-Chip Systems | Chang, En-Jui; Hsin, Hsien-Kai; Chao, Chih-Hao; Lin, Shu-Yen; Wu, An-Yeu; AN-YEU(ANDY) WU ; SHU-YEN LIN | Ieee Transactions on Computers | 28 | 26 | |
1998 | Transform-domain delayed LMS algorithm and architecture | AN-YEU(ANDY) WU ; Wu, An-Yeu; Wu, Cheng-Shing; AN-YEU(ANDY) WU | IEEE International Symposium on Circuits and Systems | | | |