第 1 到 30 筆結果,共 30 筆。
公開日期 | 標題 | 作者 | 來源出版物 | scopus | WOS | 全文 | |
---|---|---|---|---|---|---|---|
1 | 2020 | Network-cognitive traffic control: A fluidity-aware on-chip communication | Tsai, W.-C.; SAO-JIE CHEN ; Hu, Y.-H.; Chiang, M.-L. | Electronics (Switzerland) | 2 | 2 | |
2 | 2016 | A novel flow fluidity meter for BiNoC bandwidth resource allocation | Tsai, W.-C.; Lin, H.-E.; Lan, Y.-C.; Chen, S.-J.; Hu, Y.-H.; SAO-JIE CHEN | International System on Chip Conference | 2 | 0 | |
3 | 2015 | A BiNoC architecture-aware task allocation and communication scheduling scheme | Tsai, W.-C.; Chen, W.-D.; Lan, Y.-C.; Hu, Y.-H.; Chen, S.-J.; SAO-JIE CHEN | Microprocessors and Microsystems | 0 | 0 | |
4 | 2015 | A prefetching scheme for Automatic Repeat-reQuest fault-tolerant on-chip network | Tsai, W.-C.; Zheng, D.-Y.; Chen, S.-J.; Hu, Y.-H.; SAO-JIE CHEN | International Conference on Machine Learning and Cybernetics | 0 | 0 | |
5 | 2014 | 3D bidirectional-channel routing algorithm for network-based many-core embedded systems | Tsai, W.-C.; Weng, Y.-Y.; Wei, C.-J.; Chen, S.-J.; Hu, Y.-H.; SAO-JIE CHEN | Lecture Notes in Electrical Engineering | 2 | 0 | |
6 | 2014 | Bi-routing: A 3d bidirectional-channel routing algorithm for network-based many-core embedded systems | Tsai, W.-C.; Weng, Y.-Y.; Wei, C.-J.; Chen, S.-J.; Hu, Y.-H.; SAO-JIE CHEN | Journal of Computers | |||
7 | 2013 | Novel time-multiplexing bidirectional on-chip network | Wei, C.-J.; Weng, Y.-Y.; Tsai, W.-C.; Chen, S.-J.; Hu, Y.-H.; SAO-JIE CHEN | International System on Chip Conference | 1 | 0 | |
8 | 2013 | Non-minimal, turn-model based NoC routing | Tsai, W.-C.; Chu, K.-C.; Hu, Y.-H.; Chen, S.-J.; SAO-JIE CHEN | Microprocessors and Microsystems | 7 | 5 | |
9 | 2013 | A unified link-layer fault-tolerant architecture for network-based many-core embedded systems | Tsai, W.-C.; Zheng, D.-Y.; Hu, Y.-H.; Chen, S.-J.; SAO-JIE CHEN | Journal of Systems Architecture | 1 | 1 | |
10 | 2013 | Optimal fixed-point fast fourier transform | Wei, C.-J.; Liu, S.-M.; Chen, S.-J.; Hu, Y.-H.; SAO-JIE CHEN | IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation | |||
11 | 2012 | Networks on Chips: Structure and design methodologies | Tsai, W.-C.; Lan, Y.-C.; Hu, Y.-H.; Chen, S.-J.; SAO-JIE CHEN | Journal of Electrical and Computer Engineering | 60 | 0 | |
12 | 2012 | Reconfigurable networks-on-chip | Chen, S.-J.; Lan, Y.-C.; Tsai, W.-C.; Hu, Y.-H.; SAO-JIE CHEN | Reconfigurable Networks-on-Chip | 11 | 0 | |
13 | 2012 | A scalable and fault-tolerant network routing scheme for many-core and multi-chip systems | Tsai, W.-C.; Chu, K.-C.; Hu, Y.-H.; Chen, S.-J.; SAO-JIE CHEN | Journal of Parallel and Distributed Computing | 4 | 2 | |
14 | 2011 | A fault-tolerant NoC scheme using bidirectional channel | Tsai, W.-C.; Zheng, D.-Y.; Chen, S.-J.; Hu, Y.-H.; SAO-JIE CHEN | Design Automation Conference | |||
15 | 2010 | QoS aware BiNoC architecture | Lo, S.-H.; Lan, Y.-C.; Yeh, H.-H.; Tsai, W.-C.; Hu, Y.-H.; Chen, S.-J.; SAO-JIE CHEN | 2010 IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2010 | 15 | 0 | |
16 | 2010 | DyML: Dynamic Multi-Level flow control for Networks on Chip | Tsai, W.-C.; Lan, Y.-C.; Chen, S.-J.; Hu, Y.-H.; SAO-JIE CHEN | IEEE International SOC Conference, SOCC 2010 | 1 | 0 | |
17 | 2010 | Formal modeling and verification for Network-on-chip | Chen, Y.-R.; Su, W.-T.; Hsiung, P.-A.; Lan, Y.-C.; Hu, Y.-H.; Chen, S.-J.; SAO-JIE CHEN | 1st International Conference on Green Circuits and Systems, ICGCS 2010 | 18 | 0 | |
18 | 2010 | TM-FAR: Turn-model based fully adaptive routing for networks on chip | Tsai, W.-C.; Chu, K.-C.; Chen, S.-J.; Hu, Y.-H.; SAO-JIE CHEN | 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2010 | 8 | 0 | |
19 | 2010 | Optimal multiple-bit huffman decoding | Wen, Y.-N.; Lin, G.-H.; Chen, S.-J.; Hu, Y.-H.; SAO-JIE CHEN | IEEE Transactions on Circuits and Systems for Video Technology | 0 | 0 | |
20 | 2010 | ARAL-CR: An adaptive reasoning and learning cognitive radio platform | Chen, S.-J.; Hsiung, P.-A.; Yu, C.; Yen, M.-H.; Sezer, S.; Schulte, M.; Hu, Y.-H.; SAO-JIE CHEN | International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IC-SAMOS 2010 | 3 | 0 | |
21 | 2009 | BiNoC: A bidirectional NoC architecture with dynamic self-reconfigurable channel | Lan, Y.-C.; Lo, S.-H.; Lin, Y.-C.; Hu, Y.-H.; Chen, S.-J.; SAO-JIE CHEN | 3rd ACM/IEEE International Symposium on Networks-on-Chip, NoCS 2009 | 55 | 0 | |
22 | 2009 | Performance-energy tradeoffs in reliable NoCs | Lan, Y.-C.; Chen, M.C.; Chen, W.-D.; Chen, S.-J.; Hu, Y.-H.; SAO-JIE CHEN | 10th International Symposium on Quality Electronic Design, ISQED 2009 | 5 | 0 | |
23 | 2008 | Fluidity concept for NoC: A congestion avoidance and relief routing scheme | Lan, Y.-C.; Chen, M.C.; Su, A.P.; Hu, Y.-H.; Chen, S.-J.; SAO-JIE CHEN | 2008 IEEE International SOC Conference, SOCC | 9 | 0 | |
24 | 2008 | Flow maximization for NoC routing algorithms | Lan, Y.-C.; Chen, M.C.; Su, A.P.; Hu, Y.-H.; Chen, S.-J.; SAO-JIE CHEN | IEEE Computer Society Annual Symposium on VLSI: Trends in VLSI Technology and Design, ISVLSI 2008 | 3 | 0 | |
25 | 2007 | Design of a SIMD multimedia SoC platform | Lin, G.-H.; Wen, Y.-N.; Wu, X.-L.; Chen, S.-J.; Hu, Y.-H.; SAO-JIE CHEN | 20th Anniversary IEEE International SOC Conference | 3 | 0 | |
26 | 2007 | Symbolic verification and error prediction methodology | Wei, C.-J.; Lin, G.-H.; Wen, Y.-N.; Chen, S.-J.; Hu, Y.-H.; SAO-JIE CHEN | 20th Anniversary IEEE International SOC Conference | 0 | 0 | |
27 | 2007 | Optimal multiple-bit huffman decoding | Wen, Y.-N.; Chen, S.-J.; Hu, Y.-H.; SAO-JIE CHEN | 2006 IEEE International Systems-on-Chip Conference, SOC | 1 | 0 | |
28 | 2006 | Memory access optimization of motion estimation algorithms on a native SIMD PLX processor | Lin, G.-H.; Chen, S.-J.; Lee, R.B.; Hu, Y.-H.; SAO-JIE CHEN | IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS | 3 | 0 | |
29 | 2006 | Multiple-symbol parallel CAVLC decoder for H.264/AVC | Wen, Y.-N.; Wu, G.-L.; Chen, S.-J.; Hu, Y.-H.; SAO-JIE CHEN | IEEE Asia-Pacific Conference on Circuits and Systems, APCCAS | 27 | 0 | |
30 | 1994 | General area router based on planning techniques | SAO-JIE CHEN ; Tsai, C.-C.; Chen, Y.-L.; Hu, Y.-H. | IEE Proceedings: Computers and Digital Techniques | 0 | 0 |