Atomic layer deposition of sub-10?nm high-K gate dielectrics on top-gated MoS 2 transistors without surface functionalization
Journal
Applied Surface Science
Journal Volume
443
Pages
421-428
Date Issued
2018
Author(s)
Abstract
Sub-10 nm high-K gate dielectrics are of critical importance in two-dimensional transition metal dichalcogenides (TMDs) transistors. However, the chemical inertness of TMDs gives rise to a lot of pinholes in gate dielectrics, resulting in large gate leakage current. In this study, sub-10 nm, uniform and pinhole-free Al 2 O 3 high-K gate dielectrics on MoS 2 were achieved by atomic layer deposition without surface functionalization, in which an ultrathin Al 2 O 3 layer prepared with a short purge time at a low temperature of 80 °C offers the nucleation cites for the deposition of the overlaying oxide at a higher temperature. Conductive atomic force microscopy reveals the significant suppression of gate leakage current in the sub-10 nm Al 2 O 3 gate dielectrics with the low-temperature nucleation layer. Raman and X-ray photoelectron spectroscopies indicate that no oxidation occurred during the deposition of the low-temperature Al 2 O 3 nucleation layer on MoS 2 . With the high-quality sub-10 nm Al 2 O 3 high-K gate dielectrics, low hysteresis and subthreshold swing were demonstrated on the normally-off top-gated MoS 2 transistors.
Publisher
Elsevier B.V.
Type
journal article