Effects of gate-bias stress on ZnO thin-film transistors
Journal
Journal of the Society for Information Display
Journal Volume
18
Pages
802-806
Date Issued
2010-01
Author(s)
Abstract
Abstract�X The effects of gate?bias and thermal stress on the stability issues of zinc oxide thin film transistors (ZnO TFTs) deposited on glass substrates were investigated. The shift in threshold voltage for devices undergoing various post?growth annealing conditions using a stretched?exponential formalism was analyzed. The analysis indicated that the extracted parameters such as the time constant and the effective energy barrier ( E �n ) can be correlated to the device trap states associated with the annealing conditions. Improvement in the channel conductance and interface quality, hence the resultant device stability, can therefore be resumed when subject to a thermal treatment at 400�XC for 30 minutes compared with those annealed for a shorter time.
Type
journal article