Publication:
Negative capacitance enables FinFET and FDSOI scaling to 2 nm node

cris.lastimport.scopus2025-05-06T22:05:12Z
cris.virtual.departmentElectrical Engineeringen_US
cris.virtual.departmentProgram in Semiconductor Device, Material, and Hetero-integrationen_US
cris.virtual.orcid0000-0002-6216-214Xen_US
cris.virtualsource.department13c990a2-a3cf-4470-a58f-c65d06280be8
cris.virtualsource.department13c990a2-a3cf-4470-a58f-c65d06280be8
cris.virtualsource.orcid13c990a2-a3cf-4470-a58f-c65d06280be8
dc.contributor.authorHu V.P.-Hen_US
dc.contributor.authorChiu P.-Cen_US
dc.contributor.authorSachid A.Ben_US
dc.contributor.authorHu C.en_US
dc.contributor.authorVITA PI-HO HUen_US
dc.date.accessioned2021-09-02T00:07:45Z
dc.date.available2021-09-02T00:07:45Z
dc.date.issued2018
dc.description.abstractThe scaling potential of negative capacitance FinFET and FDSOI (NC-FinFET and NC-FDSOI) are studied for technology nodes down to 2nm. According to ITRS 2.0, FinFET scaling ends at 6/5nm node due to the scaling limits of fin width (6 nm Wfin) and FDSOI scaling ends at 11/10 nm due to scaling limit of the channel thickness (3 nm Tch). We present TCAD simulation evidence that using these Wfin and Tch, and negative capacitance enables FinFET and FDSOI scaling to 2 nm node. NC-FinFET and NC-FDSOI at 2 nm node show Ioff < 100nA/μm and 10%?29% higher Ion compared with 2nm FinFET(97μA/μm Ioff) and FDSOI(46μA/μm Ioff). NC-FDSOI exhibits similarly strong back-gate bias effects on Ioff and Ion compared with FDSOI. ? 2017 IEEE.
dc.identifier.doi10.1109/IEDM.2017.8268443
dc.identifier.issn01631918
dc.identifier.scopus2-s2.0-85045215162
dc.identifier.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-85045215162&doi=10.1109%2fIEDM.2017.8268443&partnerID=40&md5=7854b7a24232c8ff1df7557918b5a24c
dc.identifier.urihttps://scholars.lib.ntu.edu.tw/handle/123456789/581194
dc.relation.ispartofTechnical Digest - International Electron Devices Meeting, IEDM
dc.subjectCapacitance; Nanotechnology; Back-gate bias; Channel thickness; Fin widths; Negative capacitance; Scaling limits; TCAD simulation; Technology nodes; FinFET
dc.titleNegative capacitance enables FinFET and FDSOI scaling to 2 nm nodeen_US
dc.typeconference paper
dspace.entity.typePublication

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