Publication: Negative capacitance enables FinFET and FDSOI scaling to 2 nm node
cris.lastimport.scopus | 2025-05-06T22:05:12Z | |
cris.virtual.department | Electrical Engineering | en_US |
cris.virtual.department | Program in Semiconductor Device, Material, and Hetero-integration | en_US |
cris.virtual.orcid | 0000-0002-6216-214X | en_US |
cris.virtualsource.department | 13c990a2-a3cf-4470-a58f-c65d06280be8 | |
cris.virtualsource.department | 13c990a2-a3cf-4470-a58f-c65d06280be8 | |
cris.virtualsource.orcid | 13c990a2-a3cf-4470-a58f-c65d06280be8 | |
dc.contributor.author | Hu V.P.-H | en_US |
dc.contributor.author | Chiu P.-C | en_US |
dc.contributor.author | Sachid A.B | en_US |
dc.contributor.author | Hu C. | en_US |
dc.contributor.author | VITA PI-HO HU | en_US |
dc.date.accessioned | 2021-09-02T00:07:45Z | |
dc.date.available | 2021-09-02T00:07:45Z | |
dc.date.issued | 2018 | |
dc.description.abstract | The scaling potential of negative capacitance FinFET and FDSOI (NC-FinFET and NC-FDSOI) are studied for technology nodes down to 2nm. According to ITRS 2.0, FinFET scaling ends at 6/5nm node due to the scaling limits of fin width (6 nm Wfin) and FDSOI scaling ends at 11/10 nm due to scaling limit of the channel thickness (3 nm Tch). We present TCAD simulation evidence that using these Wfin and Tch, and negative capacitance enables FinFET and FDSOI scaling to 2 nm node. NC-FinFET and NC-FDSOI at 2 nm node show Ioff < 100nA/μm and 10%?29% higher Ion compared with 2nm FinFET(97μA/μm Ioff) and FDSOI(46μA/μm Ioff). NC-FDSOI exhibits similarly strong back-gate bias effects on Ioff and Ion compared with FDSOI. ? 2017 IEEE. | |
dc.identifier.doi | 10.1109/IEDM.2017.8268443 | |
dc.identifier.issn | 01631918 | |
dc.identifier.scopus | 2-s2.0-85045215162 | |
dc.identifier.uri | https://www.scopus.com/inward/record.uri?eid=2-s2.0-85045215162&doi=10.1109%2fIEDM.2017.8268443&partnerID=40&md5=7854b7a24232c8ff1df7557918b5a24c | |
dc.identifier.uri | https://scholars.lib.ntu.edu.tw/handle/123456789/581194 | |
dc.relation.ispartof | Technical Digest - International Electron Devices Meeting, IEDM | |
dc.subject | Capacitance; Nanotechnology; Back-gate bias; Channel thickness; Fin widths; Negative capacitance; Scaling limits; TCAD simulation; Technology nodes; FinFET | |
dc.title | Negative capacitance enables FinFET and FDSOI scaling to 2 nm node | en_US |
dc.type | conference paper | |
dspace.entity.type | Publication |