高速串列通信傳送媒介之測試
Date Issued
2003-11-30
Date
2003-11-30
Author(s)
DOI
912622E002049CC3
Abstract
Due to the limitation of clock skew, parallel communication has reached the bottleneck
in terms of data transmission. As a result, parallel communication is gradually being replaced
by high-speed serial communication. Take PC peripheral connection for example, newly
established standards like USB 2.0, Firewire (IEEE 1394), and Serial ATA, are all high-speed
serial communication standards ranging from 800 MHz to a few GHz. Due to the high clock
rate, testing of the high-speed serial communication hardware often requires pricy test
equipment and long test time, which is not efficient in a manufacturing testing environment.
As the demand of multimedia and networking applications on data bandwidth multiplies,
high-speed serial communication will become the mainstream for next-generation PCs and
future home entertainment centers. Developing high-speed serial link testing techniques will
certainly strengthen the competitive capacity of Taiwan’s industry in future electronics and
entertainment products.
The objective of this project is to develop testing techniques for high-speed serial
communication data transmission media. We will start from the serial ATA (SATA) cable,
develop for it cost-effective manufacturing testing techniques, and transfer the results to the
cooperating company. Then, we will apply the techniques to other serial communication
standards. Finally, we will study the testing of on-chip high-speed serial links. The main
research topics include (1) SATA cable fault modeling, (2) techniques for evaluating the
functional fault coverage of defect-based test set, and (3) test set selection for SATA cable.
Subjects
high-speed serial communication
analog testing
serial ATA
Publisher
臺北市：國立臺灣大學電子工程學研究所
Type
report
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