A fault-tolerant PE array based matrix multiplier design
Journal
International Symposium on VLSI Design, Automation, and Test
Date Issued
2012-04
Author(s)
Abstract
Matrix multiplication comprises a significant portion of computation efforts in many engineering and scientific applications. Realizing matrix multiplication in a two-dimensional PE (processing element) array improves computation efficiency; however, reliability and yield issues arise as the PE array complexity grows. This paper presents three fault tolerant schemes for the Cannon algorithm based two-dimensional PE array matrix multiplier. In the twisted column scheme, free PEs take over the tasks of adjacent faulty PEs; this preserves the computation efficiency. The column replacement scheme reallocates the task of a faulty column to a fault-free one; this degrades the overall performance but significantly enhances fault tolerance. The hybrid approach combines the previous two schemes; it achieves the best fault tolerance and incurs no performance degradation if the number of fault PEs is small. Simulation results and overhead analyses are presented to validate the proposed schemes.
Type
conference paper