Design-for-Test Techniques for High-Speed Data Communication Systems
Date Issued
2004-07-31
Date
2004-07-31
Author(s)
DOI
922220E002017
Abstract
The rapid deployment of gigabit I/O buffers for key communication
standards, for exmple, Gigabit Ethernet, Infiniband, 3GIO, and SONET, as
well as for high bandwidth system backplanes presents several challenges
for testing. Testing these ICs requires expensive stand-alone
bit-error-rate (BER) test sets. Cost and excessive test time make this
approach impossible for volume production. However, the industrial trend
toward higher integration levels means that gigabit serial ports can serve
as a standard I/O macro for any IC, implying that all existing VLSI
production test systems must be retrofitted with cost effective gigabit
test solutions. Thus, there is an urgent need for a cost-effective
technique to test these gigabit transceivers in volume production.
In this project, we intend to provide a low-cost DfT technique for the
jitter testing of gigibit I/O transceiver. The goal is to measure the
generated jitter at the transmitter output and the jitter tolerance at
the receiver input. This sub-project is a 3-year project. In year one,
we will first study the current gigabit communication standards and their
jitter testing requirements. After analyzing these standards, we will
perform system-level simulation to determine the jitter testing
architecture that is both flexible and can be realized on chip as the DfT
(design-for-test) circuitry. In year two, we will focus on the circuit
design of each key component. Detailed circuit-level simulation, noise
effects, and interaction with the normal functional circuits will be
performed to ensure that the added DfT circuitry has the least impact on
the system performance. In year three, a prototype IC will be fabricated.
The IC will be verified and tested to validate our ideas. Besides, we will
integrate our DfT circuitry to available gigibit I/O macros to further
validate our technique.
Subjects
high-speed serial link
jitter testing
jitter tolerance
Publisher
臺北市：國立臺灣大學電子工程學研究所
Type
report
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