A Low-Resolution Direct Digital Synthesis Transmitter Architecture Using Dithering for Multiband 5G NR Mobile Applications
Journal
IEEE Microwave and Wireless Components Letters
Journal Volume
32
Journal Issue
11
Pages
1359
Date Issued
2022-11-01
Author(s)
Abstract
This letter presents a low-resolution multiband transmitter architecture using direct digital synthesis (DDS) with dithering. Modern modulated signals constructed by a low-resolution digital-to-analog converter (DAC) suffer from quantization errors and distortions. The proposed technique reduces the quantization problems with the use of a proper oversampling ratio (OSR) and the dithering technique. This technique has lower cost and lower complexity compared to conventional transmitters while maintaining linearity performance. A 50-MHz 5G NR 256-quadratic-amplitude modulation (QAM) signal is used for concept validation at bands n1, n40, and n50. The proposed work achieved the adjacent channel leakage ratio (ACLR) and error vector magnitude (EVM) requirements of under-30 dBc and 3.5%, respectively. A single 3-bit 10-GS/s radio frequency (RF) DAC is used where the performance is similar to a conventional transmitter using a pair of 5-bit baseband in-phase and quadrature (IQ) DACs.
Subjects
Digital-to-analog converter (DAC) | dithering | quantization noise
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Type
journal article