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College of Electrical Engineering and Computer Science / 電機資訊學院
Electronics Engineering / 電子工程學研究所
An On-Chip Jitter Generation Technique for SerDes Jitter Tolerance Testing
Details
An On-Chip Jitter Generation Technique for SerDes Jitter Tolerance Testing
Journal
VLSI Design/CAD Symposium
Date Issued
2006-08
Author(s)
S.-W. Chang
J.-L. Huang
JIUN-LANG HUANG
URI
http://scholars.lib.ntu.edu.tw/handle/123456789/325754
Type
conference paper