子計畫四：類比前端電路的內建自我測試技術
Date Issued
2004-07-31
Date
2004-07-31
Author(s)
DOI
922220E002007
Abstract
The objective of this sub-project is to
develop self-testing techniques and
supporting circuitry for the analog
communication front-end circuits and the
frequency synthesizer. Without sacrificing
the system performance and inducing too
much chip area overhead, this sub-project
aims at reducing, for the single-chip wireless
transceiver, both the manufacturing test
development time and manufacturing test
cost. To reach the goal, the research topics
include (1) self-testing techniques for
AD/DA converters and frequency
synthesizers, (2) loop-back testing for
baseband analog circuits, and (3)
system-level loop-back testing.
Subjects
Design-for-Testability
Built-In
Self-Test
Self-Test
Single-chip wireless transceiver
analog front-end circuits
frequency
synthesizer
synthesizer
Publisher
臺北市：國立臺灣大學電子工程學研究所
Type
report
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