Publication: Design of CMOS Low-Noise Amplifier for Wireless LAN Applications
| dc.contributor | 呂良鴻 | en |
| dc.contributor.author | Wang, Yu-Shun | en |
| dc.creator | Wang, Yu-Shun | en |
| dc.date | 2005 | en |
| dc.date.accessioned | 2007-11-27T07:16:13Z | |
| dc.date.accessioned | 2018-07-10T01:35:40Z | |
| dc.date.available | 2007-11-27T07:16:13Z | |
| dc.date.available | 2018-07-10T01:35:40Z | |
| dc.date.issued | 2005 | |
| dc.description.abstract | The convenience introduced by the wireless technology has drastically changed the way people communicate. Other than cellular phone services, the wireless data communication has attracted great attention in recent years. In the transceiver design of a wireless LAN system, the low-power amplifier (LNA) plays an important role in the signal receiving path. It is required to provide sufficient signal amplification while maintaining a minimum noise to ensure the quality of the received signal. In this thesis, LNAs are designed and fabricated in a standard 0.18-μm CMOS technology for low-power and dual-band applications. The first CMOS LNA demonstrated is focused on its low-power and low-voltage operation. With a current-reused topology, the common-source gain stages are stacked for minimum power dissipation while achieving high small-signal gain. The fully integrated 5.7-GHz LNA exhibits 16.4-dB gain, 3.5-dB noise figure and 8-dB gain tuning range with good input and output return losses. The LNA consumes 3.2-mW dc power from a supply voltage of 1 volt. A gain/power quotient of 5.12 dB/mW is achieved in this work. Another LNA is designed to achieve dual-band operations with minimum hardware overhead. By switching the size and dc bias current of the input transistor, good input matching can be achieved. In addition, switched capacitors are used for the output matching at both frequency bands. Using the proposed design technique, a fully integrated 2.4-GHz/5.2-GHz dual-band LNA is presented. The fabricated LNA exhibits 10.1-dB gain and 2.9-dB noise figure at 2.4-GHz band, and 10.9-dB gain and 3.7-dB noise figure at 5.2-GHz band. Input and output return losses better than 10 dB are achieved at both frequency bands without external machining components. | en |
| dc.description.tableofcontents | Chapter 1 Introduction.........................1 1.1 Motivation .............................1 1.2 Thesis Organization.....................2 Chapter 2 Basic Concepts in RF Circuit Design..3 2.1 S-parameter.............................3 2.2 Power Gain..............................5 2.3 Noise Figure............................7 2.4 Sensitivity.............................9 2.5 Linearity..............................10 2.6 Summary................................15 Chapter 3 Design of a CMOS 5.7-GHz Low-Power Variable-Gain LNA...................16 3.1 Introduction...........................16 3.2 Noise Analysis of MOSFET...............17 3.3 LNA Topology...........................22 3.4 Proposed Low-Voltage Variable-Gain LNA with Current-Reused Topology...........27 3.5 Simulation Result......................30 3.6 Layout and Measurement Result..........32 3.7 Performance Comparison.................35 Chapter 4 Design of a CMOS 2.4/5.2-GHz Dual-Band LNA.......................37 4.1 Introduction...........................37 4.2 Review of Published Dual-Band LNA Topologies.............................38 4.3 Proposed Dual-Band LNA Topologies......44 4.4 Design of the Dual-Band LNA............49 4.5 Simulation Result......................52 4.6 Layout and Measurement Result..........54 4.7 Performance Summary....................58 Chapter 5 Conclusion..........................60 Reference.......................................62 | en |
| dc.format.extent | 1221388 bytes | |
| dc.format.mimetype | application/pdf | |
| dc.identifier | en-US | en |
| dc.identifier.uri | http://ntur.lib.ntu.edu.tw//handle/246246/57651 | |
| dc.identifier.uri.fulltext | http://ntur.lib.ntu.edu.tw/bitstream/246246/57651/1/ntu-94-R91943077-1.pdf | |
| dc.language | en-US | en |
| dc.language.iso | en_US | |
| dc.relation.reference | [1] B. Razavi, RF Microelectronics. Prentice Hall, 1998. [2] G. Gonzalez, Microwave Transistor Amplifiers; Analysis and Design, 2nd edition. Prentice-Hall, 1997. [3] T. H. Lee, the Design of CMOS Radio-Frequency Integrated Circuits. Cambridge University: Press, 1998. [4] D. K. Shaffer, and T. Lee, “A 1.5-V, 1.5-GHz CMOS low noise amplifier,” IEEE J. Solid-State Circuit, vol. 32, pp. 745-759, Jun 1997. [5] R. P. Jindal, “Hot-electron effects on channel thermal noise in fineline NMOS field-effect transistors,” IEEE Trans. Electron Devices, vol. ED-33, pp. 1395-1397, Sept. 1986. [6] B. Razavi, “Flicker noise in CMOS transistors from subthreshold to strong inversion at various temperatures,” IEEE Transactions on Consumer Electronics, vol. 41, pp. 1965-1971, Nov. 1994. [7] K. Ohsato, and T. Yoshimasu, “Internally matched, ultralow DC power consumption CMOS amplifier for L-band personal communications,” IEEE Microwave and Wireless Components Letters, vol. 14, no. 5, pp. 204-206, May 2004. [8] D. Linten, L. Aspemyr, W. Jeamsaksiri, J. Ramos, A. Mercha, S. Jenei, S. Thijs, R. Garcia, H. Jacobsson, P. Wambacq, S. Donnay, and S. Decoutere, “Low-power 5 GHz LNA and VCO in 90 nm RF CMOS,” IEEE VLSI Circuits Symposium, pp. 372-375, 2004. [9] T. Tsang, and M. El-Gamal, ”Gain and frequency controllable sub-1 V 5.8 GHz CMOS LNA,” IEEE International Symposium on Circuits and Systems, pp. 795-798, 2002. [10] Ming-Da Tsai, Ren-Chieh Liu, Chin-Shen Lin, and Huei Wang, ”A low-voltage fully-integrated 4.5-6-GHz CMOS variable gain low noise amplifier,” European Microwave Conference, pp. 13-16, 2003. [11] M. Raja, T. Boon, K. Kumar, and S. Wong, “A fully integrated variable gain 5.75-GHz LNA with on chip active balun for WLAN,” IEEE RFIC Symposium, pp. 439-442, 2003. [12] Yuan-Kai Chu, Che-Hong Liao, and Huey-Ru Chuang, “A 5.7-GHz 0.18-/spl mu/m CMOS gain-controlled differential LNA with current reuse for WLAN receiver,” IEEE RFIC Symposium, pp.221 – 224, June. 2003. [13] Wen-Shen Wuen and Kuei-Ann Wen, “Dual-band switchable low noise amplifier for 5-GHz wireless LAN radio receivers,” MWSCAS 2002, vol. 2, pp. II-258-II-261, Aug. 2002. [14] T. K. K. Tsang and M. N. El-Gamal, “Dual-band sub-1 V CMOS LNA for 802.11a/b WLAN applications,” ISCAS 2003, vol. 1, pp. I217-I220, May 2003. [15] Khaled M. Sharaf and Hany Y. ElHak, “A compact approach for the design of a dual-band low-noise amplifier,” MWSCAS 2001, vol. 2, pp. 890 – 893, Aug. 2001 [16] H. Hashemi and A. Hajimiri, “Concurrent multiband low-noise amplifiers-theory, design, and applications,” IEEE Transactions on Microwave Theory and Techniques, vol. 50, no. 1, pp. 288-301, Jan. 2002. [17] S. Wu and B. Razavi, “A 900-MHz/1.8-GHz CMOS receiver for dual-band applications,” IEEE J. Solid-State Circuits, vol.33, no.12, pp.2178-2185, Dec.1998. [18] K. L. Fong, “Dual-band high-linearity variable-gain low-noise amplifiers for wireless applications,” ISSCC 1999, pp. 224-225, 1999. [19] J. L. Tham et al., “A 2.7-V 900-MHz/1.9-GHz dual-band transceiver IC for digital wireless communication,” IEEE J. Solid-State Circuits, vol. 34, no. 3, pp.286-291, March 1999. [20] V. Vidojkovic et al., “Fully-integrated DECT/Bluetooth multi-band LNA in 0.18µm CMOS,” ISCAS 2004, vol. 1, pp. I-565-I-568, May 2004. [21] E. H. Westerwick, “A 5-GHz band CMOS low noise amplifier with a 2.5 dB noise figure,” VLSI Circuits Symposium 2001, pp. 224 – 227, April 2001. | en |
| dc.subject | 互補式金氧半導體 | en |
| dc.subject | 雙頻 | en |
| dc.subject | 低雜訊放大器 | en |
| dc.subject | CMOS RF | en |
| dc.subject | dual-band | en |
| dc.subject | low-noise amplifier (LNA) | en |
| dc.title | Design of CMOS Low-Noise Amplifier for Wireless LAN Applications | en |
| dc.type | thesis | en |
| dspace.entity.type | Publication |
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