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College of Electrical Engineering and Computer Science / 電機資訊學院
Electronics Engineering / 電子工程學研究所
FPGA-Based Subset Sum Delay Lines
Details
FPGA-Based Subset Sum Delay Lines
Journal
Asian Test Symposium
Pages
287-291
Date Issued
2014-01
Author(s)
C.-Y. Wang
Y.-Y. Chen
J.-L. Huang
X.-L. Huang
JIUN-LANG HUANG
DOI
10.1109/ATS.2014.60
URI
http://scholars.lib.ntu.edu.tw/handle/123456789/388845
SDGs
[SDGs]SDG7
Type
conference paper