Efficient Statistical Capacitance Variability Modeling with Orthogonal Principle Factor Analysis
Journal
ICCAD
Date Issued
2005-11
Author(s)
Abstract
Due to the ever-increasing complexity of VLSI designs and IC process technologies, the mismatch between a circuit fabricated on the wafer and the one designed in the layout tool grows ever larger. Therefore, characterizing and modeling process variations of interconnect geometry has become an integral part of analysis and optimization of modern VLSI designs. In this paper, we present a systematic methodology to develop a closed form capacitance model, which accurately captures the nonlinear relationship between parasitic capacitances and dominant global/local process variation parameters. The explicit capacitance representation applies the orthogonal principle factor analysis to greatly reduce the number of random variables associated with modeling conductor surface fluctuations while preserving the dominant sources of variations, and consequently the variational capacitance model can be efficiently utilized by statistical model order reduction and timing analysis tools. Experimental results demonstrate that the proposed method exhibits over 100× speedup compared with Monte Carlo simulation while having the advantage of generating explicit variational parasitic capacitance models of high order accuracy. ©2005 IEEE.
Subjects
Capacitance; Parasitic extraction; Principle factor analysis; Process variations; Random variable reduction
Other Subjects
Large scale systems; Mathematical models; Random processes; Statistical methods; Systems analysis; WSI circuits; Capacitance model; Parasitic extraction; Principle factor analysis; Random variable reduction; VLSI circuits
Type
conference paper