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College of Electrical Engineering and Computer Science / 電機資訊學院
Electronics Engineering / 電子工程學研究所
An Error Tolerance Scheme for 3D CMOS Imagers
Details
An Error Tolerance Scheme for 3D CMOS Imagers
Journal
Design Automation Conference
Pages
917-922
Date Issued
2010-06
Author(s)
H.-M. Sherman Chang
J.-L. Huang
D.-M. Kwai
K.-T. Tim Cheng
C.-W. Wu
JIUN-LANG HUANG
DOI
10.1145/1837274.1837505
URI
http://scholars.lib.ntu.edu.tw/handle/123456789/359565
Type
conference paper