Reconfigurable cache memory architecture for integral image and integral histogram applications
Journal
2011 IEEE Workshop on Signal Processing Systems, SiPS 2011
Pages
151-156
Date Issued
2011
Author(s)
Hsu, P.-H.
Abstract
Cache memory can reduce the memory latency between processor and off-chip DRAM, and it usually occupies a large area of the whole system. However, for accessing integral images and integral integral histograms, which are famous for getting an arbitrary-sized block summation and histogram in a constant speed and widely implemented in many applications, the read and write mechanisms of cache are not suitable for such algorithms with stream processing characteristic. In this paper, a reconfigurable cache memory architecture is proposed with two modes: normal cache mode and Row-Based Stream Processing (RBSP) mode, which is a specific memory architecture for data accessing of integral images and integral histograms. Moreover, the data reuse scheme between different filter sizes and different rows are taken into consideration to further reduce the data access to the off-chip DRAM. In addition, a method called Memory Dividing Technique (MDT) is also proposed to further reduce the word-length. SURF algorithm and center-surround histogram salience map are implemented to verify the proposed design. The experimental results show that the proposed architecture can save 89.15% and 68.12% memory read cycle count for these two applications compared to the traditional fully-associative cache in the same memory size.
Type
conference paper