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College of Electrical Engineering and Computer Science / 電機資訊學院
Electronics Engineering / 電子工程學研究所
Reconfigurable cache memory architecture for integral image and integral histogram applications
Details
Reconfigurable cache memory architecture for integral image and integral histogram applications
Journal
2011 IEEE Workshop on Signal Processing Systems, SiPS 2011
Pages
151-156
Date Issued
2011
Author(s)
Hsu, P.-H.
SHAO-YI CHIEN
DOI
10.1109/SiPS.2011.6088966
URI
http://www.scopus.com/inward/record.url?eid=2-s2.0-84055192195&partnerID=MN8TOARS
http://scholars.lib.ntu.edu.tw/handle/123456789/365124
Type
conference paper
