VLSI architecture design of guided filter for 30 frames/s full-HD Video
Journal
IEEE Transactions on Circuits and Systems for Video Technology
Journal Volume
24
Journal Issue
3
Pages
513-524
Date Issued
2014
Author(s)
Abstract
Filtering is widely used in image and video processing for various applications. Recently, the guided filter has been proposed and became one of the popular filtering methods. In this paper, to achieve the computation demand of guided filtering in full-HD video, a double integral image architecture for guided filter ASIC design is proposed. In addition, a reformation of the guided filter formula is proposed, which can prevent the error resulted from truncation in the fractional part and modify the regularization parameter on user's demand. The hardware architecture of the guided image filter is then proposed and can be embedded in mobile devices to achieve real-time HD applications. To the best of our knowledge, this paper is also the first ASIC design for guided image filter. With a TSMC 90-nm cell library, the design can operate at 100 MHz and support for Full-HD (1920 ×, 1080) 30 frame/s with 92.9K gate counts and 3.2 KB on-chip memory. Moreover, for the hardware efficiency, our architecture is also the best compared to other previous works with bilateral filter. © 2014 IEEE.
Subjects
Double integral image architecture; guided filter; integral image
Other Subjects
Hardware; Integrated circuits; Mobile devices; Double integrals; Guided filters; Hardware architecture; Hardware efficiency; Image and video processing; Integral images; Regularization parameters; VLSI architectures; Video signal processing
Type
journal article