A transistor sizing method for standard-cell optimization considering lithography effects
Journal
DTCO and Computational Patterning III
Part Of
Proceedings of SPIE - The International Society for Optical Engineering
Journal Volume
12954
ISBN (of the container)
978-151067214-7
Date Issued
2024-04-10
Author(s)
Editor(s)
Neal V. Lafferty
Harsha Grunes
Abstract
In modern digital integrated-circuit designs, standard-cell libraries are critical foundations. Transistor sizing can help determine an optimal set of transistor sizes of the standard-cell circuit under specified design constraints and desired circuit optimization goals. The conventional equation-based approaches can cause significant electric characteristic deviation, and the simulation-based approaches may be severely restricted by initial values. Recently, we proposed an improved transistor sizing method to compensate for the drawbacks. However, it did not consider the layout-dependent lithography effects. The printed wafer patterns can suffer from significant geometric distortions when layout geometry shrinks. It is worth investigating the lithography effects to ensure that the electrical characteristics of the manufactured devices can still meet the target design specifications. This work extends the effectiveness verification of the improved transistor sizing method by further considering the lithography effects. An in-house lithography simulation tool is utilized to generate wafer patterns. The electrical characteristics of transistors with non-rectangular gate shapes due to the lithography distortion are analyzed through different equivalent-gate-length estimation methods. The impacts of lithography effects on the optimized transistor sizes are characterized in several design cases.
Event(s)
DTCO and Computational Patterning III 2024
Publisher
SPIE
Type
conference paper