A transistor sizing method for standard-cell optimization considering lithography effects
Journal
DTCO and Computational Patterning III
Part Of
Proceedings of SPIE - The International Society for Optical Engineering
Journal Volume
12954
ISBN (of the container)
978-151067214-7
Date Issued
2024-04-10
Author(s)
Editor(s)
Neal V. Lafferty
Harsha Grunes
Event(s)
DTCO and Computational Patterning III 2024
Publisher
SPIE
Type
conference paper