Skip to main content
English
中文
Log In
Log in
Log in with ORCID
NTU Single Sign On
New user? Click here to register.
Have you forgotten your password?
Home
College of Electrical Engineering and Computer Science / 電機資訊學院
Electrical Engineering / 電機工程學系
Function of the Upper/Lower Parasitic BJTs in 40nm PD SOI NMOS Device due to the Back-Gate Bias Effect
Details
Function of the Upper/Lower Parasitic BJTs in 40nm PD SOI NMOS Device due to the Back-Gate Bias Effect
Journal
EUROSOI
Date Issued
2013-01
Author(s)
A. P. Chuang
S. I. Su
Z. H. Yang
J. B. Kuo
D. Chen
C. S. Yeh
JAMES-B KUO
URI
http://scholars.lib.ntu.edu.tw/handle/123456789/381392
Type
conference paper