Low-Latency Voltage-Racing Winner-Take-All (VR-WTA) Circuit for Acceleration of Learning Engine

Journal

Int. Symp. VLSI Design, Automation, and Test

Date Issued

2017

Author(s)

Chia-Heng Wu

Ting-Sheng Chen

Ding-Yuan Lee

An-Yeu (Andy) Wu

吳安宇

DOI

URI

Type

conference paper