Efficient Erase Operation by GIDL Current for 3D Structure FeFETs with Gate Stack Engineering and Compact Long-Term Retention Model
Journal
IEEE Journal of the Electron Devices Society
Journal Volume
10
Pages
115-122
Date Issued
2022
Author(s)
Abstract
We have fabricated junctionless N-type silicon-on-insulator (SOI) ferroelectric-HfO2 field effect transistors (FeFETs) with overlap and underlap structures between gate and drain/source regions to investigate the role of gate-induced-drain-leakage (GIDL) current in erase operation of FeFETs with a floating body. We also introduced a novel gate stack process for low voltage operation by inserting a Ti layer in the metal gate. The Ti layer insertion can suppress the growth of an interfacial layer (IL) by controlling oxygen intrusion into the IL during the rapid thermal anneal (RTA) process. We demonstrated an efficient erase operation at shorter and lower pulse voltage with GIDL current in the overlap structure than in the underlap structure. A compact FeFET retention model is developed based on the surface-potential based FET model, the nucleation-limited-switching (NLS) model, and the retention model of ferroelectric (FE) capacitor. Faster degradation of the program state observed in the experiment can be explained by electron detrapping according to the modeling and simulation. © 2013 IEEE.
Subjects
FeFET; Ferroelectric; GIDL; HfO2; Junctionless; Retention
Other Subjects
Drain current; Ferroelectric materials; Ferroelectricity; Field effect transistors; Hafnium oxides; Iron compounds; Silicon on insulator technology; Three dimensional displays; Titanium; Titanium compounds; Erase operation; Ferroelectric-hfo2 field effect transistor; Field-effect transistor; Gate induced drain leakage currents; Gate induced drain leakages; Junctionless; Retention.; Three-dimensional display; Logic gates
Type
journal article