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  4. Split-Gate FeFET (SG-FeFET) with Dynamic Memory Window Modulation for Non-Volatile Memory and Neuromorphic Applications
 
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Split-Gate FeFET (SG-FeFET) with Dynamic Memory Window Modulation for Non-Volatile Memory and Neuromorphic Applications

Journal
Digest of Technical Papers - Symposium on VLSI Technology
Journal Volume
2019-June
Pages
T134-T135
Date Issued
2019
Author(s)
Lin H.-H
Zheng Z.-A
Lin Z.-T
Lu Y.-C
Ho L.-Y
Lee Y.-W
Su C.-W
Su C.-J.
VITA PI-HO HU  
DOI
10.23919/VLSIT.2019.8776555
URI
https://www.scopus.com/inward/record.uri?eid=2-s2.0-85070289115&doi=10.23919%2fVLSIT.2019.8776555&partnerID=40&md5=d20a502e41cb74e10cae9fddfaa95cd1
https://scholars.lib.ntu.edu.tw/handle/123456789/581192
Abstract
In this work, we propose a novel split-gate FeFET (SG-FeFET) with two separate external gates to dynamically modulate the memory window (MW) for non-volatile memory and neuromorphic applications. During read operation, only one gate is turned on to decrease the area ratio (AFE/AIL) of ferroelectric layer to insulator layer, which increases MW and read current ratio (IRead-1/IRead-0). During write operation (program/erase), both two gates are turned on to increase AFE/AIL, which decreases MW, thereby resulting in lower write voltage (VWrite). Compared to FeFET, SG-FeFET (1) Demonstrates lower VWrite ( =1.85V) and 59.5% reduction in write energy at fixed IRead-1/IRead-0; (2) Exhibits lower read energy (-11.3%) and higher IRead-1/IRead-0 (=8.6E6) at fixed VWrite; (3) Allows random access and eliminates half-select disturb; (4) Preserves higher endurance due to lower VWrite and charge trapping. SG-FeFET as synaptic device also exhibits superior symmetry and linearity for potentiation and depression process. ? 2019 The Japan Society of Applied Physics.
Subjects
ferroelectric FET; memory window; neuromorphic; non-volatile memory; Split-gate; synaptic device; write energy
Other Subjects
Charge trapping; Ferroelectricity; Nonvolatile storage; Memory window; Neuromorphic; Non-volatile memory; Split gates; synaptic device; write energy; VLSI circuits
Type
conference paper

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