Parallel order ATPG for test compaction
Journal
2018 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2018
Pages
1月4日
Date Issued
2018
Author(s)
Abstract
In this paper, we proposed a novel test compaction algorithm, called Parallel Order Dynamic Test Compaction (PO-DTC). We show that the order of secondary faults within a single test generation is important for test compaction. We launch parallel ATPG with different orders of secondary faults and choose the best test pattern with the largest number of detected faults. Experimental results show that our test length is 48% shorter than that of a highly compacted commercial ATPG. Our test length is the smallest among all previous work published so far. Our test length for N-detect test sets is at least 1/4 shorter than that of the commercial ATPG.
Type
conference paper